core: upgrade from write32() to io_write32() and friends

Replace use of readX() and writeX() with io_readX() and io_writeX().
The former function are about to be deprecated in favor to the later.

This change upgrades core generic code and drivers.
At some place, io_clrbitsX(), io_setbitsX() and io_clrsetbitsX()
replace the writeX(readX() ...) operations when obvious.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

24 files changed, 268 insertions, 292 deletions

diff --git a/core/arch/arm/mm/tee_pager.c b/core/arch/arm/mm/tee_pager.c
index cc196123..4d171918 100644
--- a/core/arch/arm/mm/tee_pager.c
+++ b/core/arch/arm/mm/tee_pager.c
@@ -232,8 +232,8 @@ static uint32_t pager_lock_check_stack(size_t stack_size)
 		 * the thread.
 		 */
 		for (n = 0; n < stack_size; n += SMALL_PAGE_SIZE)
-			write8(1, (vaddr_t)buf + n);
-		write8(1, (vaddr_t)buf + stack_size - 1);
+			io_write8((vaddr_t)buf + n, 1);
+		io_write8((vaddr_t)buf + stack_size - 1, 1);
 	}
 
 	return pager_lock(NULL);
diff --git a/core/drivers/atmel_uart.c b/core/drivers/atmel_uart.c
index 82ebd938..2f68fa6a 100644
--- a/core/drivers/atmel_uart.c
+++ b/core/drivers/atmel_uart.c
@@ -61,7 +61,7 @@ static void atmel_uart_flush(struct serial_chip *chip)
 {
 	vaddr_t base = chip_to_base(chip);
 
-	while (!(read32(base + ATMEL_UART_SR) & ATMEL_SR_TXEMPTY))
+	while (!(io_read32(base + ATMEL_UART_SR) & ATMEL_SR_TXEMPTY))
 		;
 }
 
@@ -69,20 +69,20 @@ static int atmel_uart_getchar(struct serial_chip *chip)
 {
 	vaddr_t base = chip_to_base(chip);
 
-	while (read32(base + ATMEL_UART_SR) & ATMEL_SR_RXRDY)
+	while (io_read32(base + ATMEL_UART_SR) & ATMEL_SR_RXRDY)
 		;
 
-	return read32(base + ATMEL_UART_RHR);
+	return io_read32(base + ATMEL_UART_RHR);
 }
 
 static void atmel_uart_putc(struct serial_chip *chip, int ch)
 {
 	vaddr_t base = chip_to_base(chip);
 
-	while (!(read32(base + ATMEL_UART_SR) & ATMEL_SR_TXRDY))
+	while (!(io_read32(base + ATMEL_UART_SR) & ATMEL_SR_TXRDY))
 		;
 
-	write32(ch, base + ATMEL_UART_THR);
+	io_write32(base + ATMEL_UART_THR, ch);
 }
 
 static const struct serial_ops atmel_uart_ops = {
diff --git a/core/drivers/cdns_uart.c b/core/drivers/cdns_uart.c
index 75985193..342cf11c 100644
--- a/core/drivers/cdns_uart.c
+++ b/core/drivers/cdns_uart.c
@@ -67,7 +67,7 @@ static void cdns_uart_flush(struct serial_chip *chip)
 {
 	vaddr_t base = chip_to_base(chip);
 
-	while (!(read32(base + CDNS_UART_CHANNEL_STATUS) &
+	while (!(io_read32(base + CDNS_UART_CHANNEL_STATUS) &
 		 CDNS_UART_CHANNEL_STATUS_TEMPTY))
 		;
 }
@@ -76,8 +76,8 @@ static bool cdns_uart_have_rx_data(struct serial_chip *chip)
 {
 	vaddr_t base = chip_to_base(chip);
 
-	return !(read32(base + CDNS_UART_CHANNEL_STATUS) &
-			CDNS_UART_CHANNEL_STATUS_REMPTY);
+	return !(io_read32(base + CDNS_UART_CHANNEL_STATUS) &
+		 CDNS_UART_CHANNEL_STATUS_REMPTY);
 }
 
 static int cdns_uart_getchar(struct serial_chip *chip)
@@ -86,7 +86,7 @@ static int cdns_uart_getchar(struct serial_chip *chip)
 
 	while (!cdns_uart_have_rx_data(chip))
 		;
-	return read32(base + CDNS_UART_FIFO) & 0xff;
+	return io_read32(base + CDNS_UART_FIFO) & 0xff;
 }
 
 static void cdns_uart_putc(struct serial_chip *chip, int ch)
@@ -94,12 +94,12 @@ static void cdns_uart_putc(struct serial_chip *chip, int ch)
 	vaddr_t base = chip_to_base(chip);
 
 	/* Wait until there is space in the FIFO */
-	while (read32(base + CDNS_UART_CHANNEL_STATUS) &
-			CDNS_UART_CHANNEL_STATUS_TFUL)
+	while (io_read32(base + CDNS_UART_CHANNEL_STATUS) &
+	       CDNS_UART_CHANNEL_STATUS_TFUL)
 		;
 
 	/* Send the character */
-	write32(ch, base + CDNS_UART_FIFO);
+	io_write32(base + CDNS_UART_FIFO, ch);
 }
 
 
@@ -125,8 +125,8 @@ void cdns_uart_init(struct cdns_uart_data *pd, paddr_t base, uint32_t uart_clk,
 		return;
 
 	/* Enable UART and RX/TX */
-	write32(CDNS_UART_CONTROL_RXEN | CDNS_UART_CONTROL_TXEN,
-		base + CDNS_UART_CONTROL);
+	io_write32(base + CDNS_UART_CONTROL,
+		   CDNS_UART_CONTROL_RXEN | CDNS_UART_CONTROL_TXEN);
 
 	cdns_uart_flush(&pd->chip);
 }
diff --git a/core/drivers/dra7_rng.c b/core/drivers/dra7_rng.c
index 386c86cd..fd36a69f 100644
--- a/core/drivers/dra7_rng.c
+++ b/core/drivers/dra7_rng.c
@@ -87,29 +87,30 @@ uint8_t hw_get_random_byte(void)
 
 	if (!pos) {
 		/* Is the result ready (available)? */
-		while (!(read32(rng + RNG_STATUS) & RNG_READY)) {
+		while (!(io_read32(rng + RNG_STATUS) & RNG_READY)) {
 			/* Is the shutdown threshold reached? */
-			if (read32(rng + RNG_STATUS) & SHUTDOWN_OFLO) {
-				uint32_t alarm = read32(rng + RNG_ALARMSTOP);
-				uint32_t tuning = read32(rng + RNG_FRODETUNE);
+			if (io_read32(rng + RNG_STATUS) & SHUTDOWN_OFLO) {
+				uint32_t alarm = io_read32(rng + RNG_ALARMSTOP);
+				uint32_t tune = io_read32(rng + RNG_FRODETUNE);
+
 				/* Clear the alarm events */
-				write32(0x0, rng + RNG_ALARMMASK);
-				write32(0x0, rng + RNG_ALARMSTOP);
+				io_write32(rng + RNG_ALARMMASK, 0x0);
+				io_write32(rng + RNG_ALARMSTOP, 0x0);
 				/* De-tune offending FROs */
-				write32(tuning ^ alarm, rng + RNG_FRODETUNE);
+				io_write32(rng + RNG_FRODETUNE, tune ^ alarm);
 				/* Re-enable the shut down FROs */
-				write32(RNG_FRO_MASK, rng + RNG_FROENABLE);
+				io_write32(rng + RNG_FROENABLE, RNG_FRO_MASK);
 				/* Clear the shutdown overflow event */
-				write32(SHUTDOWN_OFLO, rng + RNG_INTACK);
+				io_write32(rng + RNG_INTACK, SHUTDOWN_OFLO);
 
 				DMSG("Fixed FRO shutdown\n");
 			}
 		}
 		/* Read random value */
-		random.val[0] = read32(rng + RNG_OUTPUT_L);
-		random.val[1] = read32(rng + RNG_OUTPUT_H);
+		random.val[0] = io_read32(rng + RNG_OUTPUT_L);
+		random.val[1] = io_read32(rng + RNG_OUTPUT_H);
 		/* Acknowledge read complete */
-		write32(RNG_READY, rng + RNG_INTACK);
+		io_write32(rng + RNG_INTACK, RNG_READY);
 	}
 
 	ret = random.byte[pos];
@@ -128,14 +129,14 @@ static TEE_Result dra7_rng_init(void)
 	uint32_t val;
 
 	/* Execute a software reset */
-	write32(RNG_SOFT_RESET, rng + RNG_SOFT_RESET_REG);
+	io_write32(rng + RNG_SOFT_RESET_REG, RNG_SOFT_RESET);
 
 	/* Wait for the software reset completion by polling */
-	while (read32(rng + RNG_SOFT_RESET_REG) & RNG_SOFT_RESET)
+	while (io_read32(rng + RNG_SOFT_RESET_REG) & RNG_SOFT_RESET)
 		;
 
 	/* Switch to low-power operating mode */
-	write32(RNG_AUTOIDLE, rng + RNG_SYS_CONFIG_REG);
+	io_write32(rng + RNG_SYS_CONFIG_REG, RNG_AUTOIDLE);
 
 	/*
 	 * Select the number of clock input cycles to the
@@ -148,13 +149,13 @@ static TEE_Result dra7_rng_init(void)
 			RNG_CONFIG_MIN_REFIL_CYCLES_SHIFT;
 	val |= RNG_CONFIG_MAX_REFIL_CYCLES <<
 			RNG_CONFIG_MAX_REFIL_CYCLES_SHIFT;
-	write32(val, rng + RNG_CONFIG);
+	io_write32(rng + RNG_CONFIG, val);
 
 	/* Configure the desired FROs */
-	write32(0x0, rng + RNG_FRODETUNE);
+	io_write32(rng + RNG_FRODETUNE, 0x0);
 
 	/* Enable all FROs */
-	write32(0xffffff, rng + RNG_FROENABLE);
+	io_write32(rng + RNG_FROENABLE, 0xffffff);
 
 	/*
 	 * Select the maximum number of samples after
@@ -168,12 +169,12 @@ static TEE_Result dra7_rng_init(void)
 	 * allowed to be shut downed
 	 */
 	val |= RNG_SHUTDOWN_THRESHOLD << RNG_ALARMCNT_SHUTDOWN_TH_SHIFT;
-	write32(val, rng + RNG_ALARMCNT);
+	io_write32(rng + RNG_ALARMCNT, val);
 
 	/* Enable the RNG module */
 	val = RNG_CONTROL_STARTUP_CYCLES << RNG_CONTROL_STARTUP_CYCLES_SHIFT;
 	val |= ENABLE_TRNG;
-	write32(val, rng + RNG_CONTROL);
+	io_write32(rng + RNG_CONTROL, val);
 
 	IMSG("DRA7x TRNG initialized");
 
diff --git a/core/drivers/gic.c b/core/drivers/gic.c
index 9b4948c4..9735ae53 100644
--- a/core/drivers/gic.c
+++ b/core/drivers/gic.c
@@ -99,18 +99,18 @@ static size_t probe_max_it(vaddr_t gicc_base __maybe_unused, vaddr_t gicd_base)
 	old_ctlr = read_icc_ctlr();
 	write_icc_ctlr(0);
 #else
-	old_ctlr = read32(gicc_base + GICC_CTLR);
-	write32(0, gicc_base + GICC_CTLR);
+	old_ctlr = io_read32(gicc_base + GICC_CTLR);
+	io_write32(gicc_base + GICC_CTLR, 0);
 #endif
 	for (i = max_regs; i >= 0; i--) {
 		uint32_t old_reg;
 		uint32_t reg;
 		int b;
 
-		old_reg = read32(gicd_base + GICD_ISENABLER(i));
-		write32(0xffffffff, gicd_base + GICD_ISENABLER(i));
-		reg = read32(gicd_base + GICD_ISENABLER(i));
-		write32(~old_reg, gicd_base + GICD_ICENABLER(i));
+		old_reg = io_read32(gicd_base + GICD_ISENABLER(i));
+		io_write32(gicd_base + GICD_ISENABLER(i), 0xffffffff);
+		reg = io_read32(gicd_base + GICD_ISENABLER(i));
+		io_write32(gicd_base + GICD_ICENABLER(i), ~old_reg);
 		for (b = NUM_INTS_PER_REG - 1; b >= 0; b--) {
 			if (BIT32(b) & reg) {
 				ret = i * NUM_INTS_PER_REG + b;
@@ -122,7 +122,7 @@ out:
 #if defined(CFG_ARM_GICV3)
 	write_icc_ctlr(old_ctlr);
 #else
-	write32(old_ctlr, gicc_base + GICC_CTLR);
+	io_write32(gicc_base + GICC_CTLR, old_ctlr);
 #endif
 	return ret;
 }
@@ -140,7 +140,7 @@ void gic_cpu_init(struct gic_data *gd)
 	 * ID8-ID15(SGI)  for Secure interrupts.
 	 * All PPI config as Non-secure interrupts.
 	 */
-	write32(0xffff00ff, gd->gicd_base + GICD_IGROUPR(0));
+	io_write32(gd->gicd_base + GICD_IGROUPR(0), 0xffff00ff);
 
 	/* Set the priority mask to permit Non-secure interrupts, and to
 	 * allow the Non-secure world to adjust the priority mask itself
@@ -150,11 +150,12 @@ void gic_cpu_init(struct gic_data *gd)
 	write_icc_ctlr(GICC_CTLR_ENABLEGRP0 | GICC_CTLR_ENABLEGRP1 |
 		       GICC_CTLR_FIQEN);
 #else
-	write32(0x80, gd->gicc_base + GICC_PMR);
+	io_write32(gd->gicc_base + GICC_PMR, 0x80);
 
 	/* Enable GIC */
-	write32(GICC_CTLR_ENABLEGRP0 | GICC_CTLR_ENABLEGRP1 | GICC_CTLR_FIQEN,
-		gd->gicc_base + GICC_CTLR);
+	io_write32(gd->gicc_base + GICC_CTLR,
+		   GICC_CTLR_ENABLEGRP0 | GICC_CTLR_ENABLEGRP1 |
+		   GICC_CTLR_FIQEN);
 #endif
 }
 
@@ -167,10 +168,10 @@ void gic_init(struct gic_data *gd, vaddr_t gicc_base __maybe_unused,
 
 	for (n = 0; n <= gd->max_it / NUM_INTS_PER_REG; n++) {
 		/* Disable interrupts */
-		write32(0xffffffff, gd->gicd_base + GICD_ICENABLER(n));
+		io_write32(gd->gicd_base + GICD_ICENABLER(n), 0xffffffff);
 
 		/* Make interrupts non-pending */
-		write32(0xffffffff, gd->gicd_base + GICD_ICPENDR(n));
+		io_write32(gd->gicd_base + GICD_ICPENDR(n), 0xffffffff);
 
 		/* Mark interrupts non-secure */
 		if (n == 0) {
@@ -179,9 +180,9 @@ void gic_init(struct gic_data *gd, vaddr_t gicc_base __maybe_unused,
                          * ID8-ID15(SGI)  for Secure interrupts.
                          * All PPI config as Non-secure interrupts.
 			 */
-			write32(0xffff00ff, gd->gicd_base + GICD_IGROUPR(n));
+			io_write32(gd->gicd_base + GICD_IGROUPR(n), 0xffff00ff);
 		} else {
-			write32(0xffffffff, gd->gicd_base + GICD_IGROUPR(n));
+			io_write32(gd->gicd_base + GICD_IGROUPR(n), 0xffffffff);
 		}
 	}
 
@@ -193,14 +194,14 @@ void gic_init(struct gic_data *gd, vaddr_t gicc_base __maybe_unused,
 	write_icc_ctlr(GICC_CTLR_ENABLEGRP0 | GICC_CTLR_ENABLEGRP1 |
 		       GICC_CTLR_FIQEN);
 #else
-	write32(0x80, gd->gicc_base + GICC_PMR);
+	io_write32(gd->gicc_base + GICC_PMR, 0x80);
 
 	/* Enable GIC */
-	write32(GICC_CTLR_ENABLEGRP0 | GICC_CTLR_ENABLEGRP1 | GICC_CTLR_FIQEN,
-		gd->gicc_base + GICC_CTLR);
+	io_write32(gd->gicc_base + GICC_CTLR, GICC_CTLR_FIQEN |
+		   GICC_CTLR_ENABLEGRP0 | GICC_CTLR_ENABLEGRP1);
 #endif
-	write32(read32(gd->gicd_base + GICD_CTLR) | GICD_CTLR_ENABLEGRP0 |
-		GICD_CTLR_ENABLEGRP1, gd->gicd_base + GICD_CTLR);
+	io_setbits32(gd->gicd_base + GICD_CTLR,
+		     GICD_CTLR_ENABLEGRP0 | GICD_CTLR_ENABLEGRP1);
 }
 
 void gic_init_base_addr(struct gic_data *gd, vaddr_t gicc_base __maybe_unused,
@@ -218,12 +219,11 @@ static void gic_it_add(struct gic_data *gd, size_t it)
 	uint32_t mask = 1 << (it % NUM_INTS_PER_REG);
 
 	/* Disable the interrupt */
-	write32(mask, gd->gicd_base + GICD_ICENABLER(idx));
+	io_write32(gd->gicd_base + GICD_ICENABLER(idx), mask);
 	/* Make it non-pending */
-	write32(mask, gd->gicd_base + GICD_ICPENDR(idx));
+	io_write32(gd->gicd_base + GICD_ICPENDR(idx), mask);
 	/* Assign it to group0 */
-	write32(read32(gd->gicd_base + GICD_IGROUPR(idx)) & ~mask,
-			gd->gicd_base + GICD_IGROUPR(idx));
+	io_clrbits32(gd->gicd_base + GICD_IGROUPR(idx), mask);
 }
 
 static void gic_it_set_cpu_mask(struct gic_data *gd, size_t it,
@@ -232,22 +232,20 @@ static void gic_it_set_cpu_mask(struct gic_data *gd, size_t it,
 	size_t idx __maybe_unused = it / NUM_INTS_PER_REG;
 	uint32_t mask __maybe_unused = 1 << (it % NUM_INTS_PER_REG);
 	uint32_t target, target_shift;
+	vaddr_t itargetsr = gd->gicd_base +
+			    GICD_ITARGETSR(it / NUM_TARGETS_PER_REG);
 
 	/* Assigned to group0 */
-	assert(!(read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask));
+	assert(!(io_read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask));
 
 	/* Route it to selected CPUs */
-	target = read32(gd->gicd_base +
-			GICD_ITARGETSR(it / NUM_TARGETS_PER_REG));
+	target = io_read32(itargetsr);
 	target_shift = (it % NUM_TARGETS_PER_REG) * ITARGETSR_FIELD_BITS;
 	target &= ~(ITARGETSR_FIELD_MASK << target_shift);
 	target |= cpu_mask << target_shift;
-	DMSG("cpu_mask: writing 0x%x to 0x%" PRIxVA,
-	     target, gd->gicd_base + GICD_ITARGETSR(it / NUM_TARGETS_PER_REG));
-	write32(target,
-		gd->gicd_base + GICD_ITARGETSR(it / NUM_TARGETS_PER_REG));
-	DMSG("cpu_mask: 0x%x\n",
-	     read32(gd->gicd_base + GICD_ITARGETSR(it / NUM_TARGETS_PER_REG)));
+	DMSG("cpu_mask: writing 0x%x to 0x%" PRIxVA, target, itargetsr);
+	io_write32(itargetsr, target);
+	DMSG("cpu_mask: 0x%x", io_read32(itargetsr));
 }
 
 static void gic_it_set_prio(struct gic_data *gd, size_t it, uint8_t prio)
@@ -256,31 +254,32 @@ static void gic_it_set_prio(struct gic_data *gd, size_t it, uint8_t prio)
 	uint32_t mask __maybe_unused = 1 << (it % NUM_INTS_PER_REG);
 
 	/* Assigned to group0 */
-	assert(!(read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask));
+	assert(!(io_read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask));
 
 	/* Set prio it to selected CPUs */
 	DMSG("prio: writing 0x%x to 0x%" PRIxVA,
 		prio, gd->gicd_base + GICD_IPRIORITYR(0) + it);
-	write8(prio, gd->gicd_base + GICD_IPRIORITYR(0) + it);
+	io_write8(gd->gicd_base + GICD_IPRIORITYR(0) + it, prio);
 }
 
 static void gic_it_enable(struct gic_data *gd, size_t it)
 {
 	size_t idx = it / NUM_INTS_PER_REG;
 	uint32_t mask = 1 << (it % NUM_INTS_PER_REG);
+	vaddr_t base = gd->gicd_base;
 
 	/* Assigned to group0 */
-	assert(!(read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask));
+	assert(!(io_read32(base + GICD_IGROUPR(idx)) & mask));
 	if (it >= NUM_SGI) {
 		/*
 		 * Not enabled yet, except Software Generated Interrupt
 		 * which is implementation defined
 		 */
-		assert(!(read32(gd->gicd_base + GICD_ISENABLER(idx)) & mask));
+		assert(!(io_read32(base + GICD_ISENABLER(idx)) & mask));
 	}
 
 	/* Enable the interrupt */
-	write32(mask, gd->gicd_base + GICD_ISENABLER(idx));
+	io_write32(base + GICD_ISENABLER(idx), mask);
 }
 
 static void gic_it_disable(struct gic_data *gd, size_t it)
@@ -289,10 +288,10 @@ static void gic_it_disable(struct gic_data *gd, size_t it)
 	uint32_t mask = 1 << (it % NUM_INTS_PER_REG);
 
 	/* Assigned to group0 */
-	assert(!(read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask));
+	assert(!(io_read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask));
 
 	/* Disable the interrupt */
-	write32(mask, gd->gicd_base + GICD_ICENABLER(idx));
+	io_write32(gd->gicd_base + GICD_ICENABLER(idx), mask);
 }
 
 static void gic_it_set_pending(struct gic_data *gd, size_t it)
@@ -303,10 +302,10 @@ static void gic_it_set_pending(struct gic_data *gd, size_t it)
 	/* Should be Peripheral Interrupt */
 	assert(it >= NUM_SGI);
 	/* Assigned to group0 */
-	assert(!(read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask));
+	assert(!(io_read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask));
 
 	/* Raise the interrupt */
-	write32(mask, gd->gicd_base + GICD_ISPENDR(idx));
+	io_write32(gd->gicd_base + GICD_ISPENDR(idx), mask);
 }
 
 static void gic_it_raise_sgi(struct gic_data *gd, size_t it,
@@ -322,7 +321,7 @@ static void gic_it_raise_sgi(struct gic_data *gd, size_t it,
 	assert(it < NUM_SGI);
 
 	/* Raise the interrupt */
-	write32(mask, gd->gicd_base + GICD_SGIR);
+	io_write32(gd->gicd_base + GICD_SGIR, mask);
 }
 
 static uint32_t gic_read_iar(struct gic_data *gd __maybe_unused)
@@ -330,7 +329,7 @@ static uint32_t gic_read_iar(struct gic_data *gd __maybe_unused)
 #if defined(CFG_ARM_GICV3)
 	return read_icc_iar1();
 #else
-	return read32(gd->gicc_base + GICC_IAR);
+	return io_read32(gd->gicc_base + GICC_IAR);
 #endif
 }
 
@@ -339,7 +338,7 @@ static void gic_write_eoir(struct gic_data *gd __maybe_unused, uint32_t eoir)
 #if defined(CFG_ARM_GICV3)
 	write_icc_eoir1(eoir);
 #else
-	write32(eoir, gd->gicc_base + GICC_EOIR);
+	io_write32(gd->gicc_base + GICC_EOIR, eoir);
 #endif
 }
 
@@ -347,14 +346,14 @@ static bool gic_it_is_enabled(struct gic_data *gd, size_t it)
 {
 	size_t idx = it / NUM_INTS_PER_REG;
 	uint32_t mask = 1 << (it % NUM_INTS_PER_REG);
-	return !!(read32(gd->gicd_base + GICD_ISENABLER(idx)) & mask);
+	return !!(io_read32(gd->gicd_base + GICD_ISENABLER(idx)) & mask);
 }
 
 static bool __maybe_unused gic_it_get_group(struct gic_data *gd, size_t it)
 {
 	size_t idx = it / NUM_INTS_PER_REG;
 	uint32_t mask = 1 << (it % NUM_INTS_PER_REG);
-	return !!(read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask);
+	return !!(io_read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask);
 }
 
 static uint32_t __maybe_unused gic_it_get_target(struct gic_data *gd, size_t it)
@@ -363,11 +362,9 @@ static uint32_t __maybe_unused gic_it_get_target(struct gic_data *gd, size_t it)
 	uint32_t target_shift = (it % NUM_TARGETS_PER_REG) *
 				ITARGETSR_FIELD_BITS;
 	uint32_t target_mask = ITARGETSR_FIELD_MASK << target_shift;
-	uint32_t target =
-		read32(gd->gicd_base + GICD_ITARGETSR(reg_idx)) & target_mask;
+	uint32_t target = io_read32(gd->gicd_base + GICD_ITARGETSR(reg_idx));
 
-	target = target >> target_shift;
-	return target;
+	return (target & target_mask) >> target_shift;
 }
 
 void gic_dump_state(struct gic_data *gd)
@@ -377,9 +374,9 @@ void gic_dump_state(struct gic_data *gd)
 #if defined(CFG_ARM_GICV3)
 	DMSG("GICC_CTLR: 0x%x", read_icc_ctlr());
 #else
-	DMSG("GICC_CTLR: 0x%x", read32(gd->gicc_base + GICC_CTLR));
+	DMSG("GICC_CTLR: 0x%x", io_read32(gd->gicc_base + GICC_CTLR));
 #endif
-	DMSG("GICD_CTLR: 0x%x", read32(gd->gicd_base + GICD_CTLR));
+	DMSG("GICD_CTLR: 0x%x", io_read32(gd->gicd_base + GICD_CTLR));
 
 	for (i = 0; i < (int)gd->max_it; i++) {
 		if (gic_it_is_enabled(gd, i)) {
diff --git a/core/drivers/hi16xx_rng.c b/core/drivers/hi16xx_rng.c
index 41269d2e..3d2d367a 100644
--- a/core/drivers/hi16xx_rng.c
+++ b/core/drivers/hi16xx_rng.c
@@ -44,17 +44,17 @@ static TEE_Result hi16xx_rng_init(void)
 	TEE_Time time;
 
 	/* ALG sub-controller must allow RNG out of reset */
-	write32(ALG_SC_SRST_DREQ_RNG, alg + ALG_SC_RNG_RESET_DREQ);
+	io_write32(alg + ALG_SC_RNG_RESET_DREQ, ALG_SC_SRST_DREQ_RNG);
 
 	/* Set initial seed */
 	tee_time_get_sys_time(&time);
-	write32(time.seconds * 1000 + time.millis, rng + RNG_SEED);
+	io_write32(rng + RNG_SEED, time.seconds * 1000 + time.millis);
 
 	/*
 	 * Enable RNG and configure it to re-seed automatically from the
 	 * internal ring oscillator
 	 */
-	write32(RNG_EN | RNG_RING_EN | RNG_SEED_SEL, rng + RNG_CTRL);
+	io_write32(rng + RNG_CTRL, RNG_EN | RNG_RING_EN | RNG_SEED_SEL);
 
 	IMSG("Hi16xx RNG initialized");
 	return TEE_SUCCESS;
@@ -77,7 +77,7 @@ uint8_t hw_get_random_byte(void)
 		r = (vaddr_t)phys_to_virt(RNG_BASE, MEM_AREA_IO_SEC) + RNG_NUM;
 
 	if (!pos)
-		random.val = read32(r);
+		random.val = io_read32(r);
 
 	ret = random.byte[pos++];
 
diff --git a/core/drivers/hi16xx_uart.c b/core/drivers/hi16xx_uart.c
index 0673af18..a0cf62a6 100644
--- a/core/drivers/hi16xx_uart.c
+++ b/core/drivers/hi16xx_uart.c
@@ -70,7 +70,7 @@ static void hi16xx_uart_flush(struct serial_chip *chip)
 {
 	vaddr_t base = chip_to_base(chip);
 
-	while (!(read32(base + UART_USR) & UART_USR_TFE_BIT))
+	while (!(io_read32(base + UART_USR) & UART_USR_TFE_BIT))
 		;
 }
 
@@ -79,18 +79,18 @@ static void hi16xx_uart_putc(struct serial_chip *chip, int ch)
 	vaddr_t base = chip_to_base(chip);
 
 	/* Wait until TX FIFO is empty */
-	while (!(read32(base + UART_USR) & UART_USR_TFE_BIT))
+	while (!(io_read32(base + UART_USR) & UART_USR_TFE_BIT))
 		;
 
 	/* Put character into TX FIFO */
-	write32(ch & 0xFF, base + UART_THR);
+	io_write32(base + UART_THR, ch & 0xFF);
 }
 
 static bool hi16xx_uart_have_rx_data(struct serial_chip *chip)
 {
 	vaddr_t base = chip_to_base(chip);
 
-	return (read32(base + UART_USR) & UART_USR_RFNE_BIT);
+	return (io_read32(base + UART_USR) & UART_USR_RFNE_BIT);
 }
 
 static int hi16xx_uart_getchar(struct serial_chip *chip)
@@ -99,7 +99,7 @@ static int hi16xx_uart_getchar(struct serial_chip *chip)
 
 	while (!hi16xx_uart_have_rx_data(chip))
 		;
-	return read32(base + UART_RBR) & 0xFF;
+	return io_read32(base + UART_RBR) & 0xFF;
 }
 
 static const struct serial_ops hi16xx_uart_ops = {
@@ -119,22 +119,22 @@ void hi16xx_uart_init(struct hi16xx_uart_data *pd, paddr_t base,
 	pd->chip.ops = &hi16xx_uart_ops;
 
 	/* Enable (and clear) FIFOs */
-	write32(UART_FCR_FIFO_EN, base + UART_FCR);
+	io_write32(base + UART_FCR, UART_FCR_FIFO_EN);
 
 	/* Enable access to _DLL and _DLH */
-	write32(UART_LCR_DLAB, base + UART_LCR);
+	io_write32(base + UART_LCR, UART_LCR_DLAB);
 
 	/* Calculate and set UART_DLL */
-	write32(freq_div & 0xFF, base + UART_DLL);
+	io_write32(base + UART_DLL, freq_div & 0xFF);
 
 	/* Calculate and set UART_DLH */
-	write32((freq_div >> 8) & 0xFF, base + UART_DLH);
+	io_write32(base + UART_DLH, (freq_div >> 8) & 0xFF);
 
 	/* Clear _DLL/_DLH access bit, set data size (8 bits), parity etc. */
-	write32(UART_LCR_DLS8, base + UART_LCR);
+	io_write32(base + UART_LCR, UART_LCR_DLS8);
 
 	/* Disable interrupt mode */
-	write32(0, base + UART_IEL);
+	io_write32(base + UART_IEL, 0);
 
 	hi16xx_uart_flush(&pd->chip);
 }
diff --git a/core/drivers/imx_snvs.c b/core/drivers/imx_snvs.c
index 278d42f9..3b82ebe9 100644
--- a/core/drivers/imx_snvs.c
+++ b/core/drivers/imx_snvs.c
@@ -93,16 +93,16 @@ static uint64_t snvs_srtc_read_lp_counter(void)
 	uint32_t val;
 
 	do {
-		val = read32(snvs + SNVS_LPSRTCMR);
+		val = io_read32(snvs + SNVS_LPSRTCMR);
 		val1 = val;
 		val1 <<= 32;
-		val = read32(snvs + SNVS_LPSRTCLR);
+		val = io_read32(snvs + SNVS_LPSRTCLR);
 		val1 |= val;
 
-		val = read32(snvs + SNVS_LPSRTCMR);
+		val = io_read32(snvs + SNVS_LPSRTCMR);
 		val2 = val;
 		val2 <<= 32;
-		val = read32(snvs + SNVS_LPSRTCLR);
+		val = io_read32(snvs + SNVS_LPSRTCLR);
 		val2 |= val;
 
 	/*
@@ -140,12 +140,12 @@ TEE_Result snvs_srtc_enable(void)
 	int timeout = 2000;
 	uint32_t val;
 
-	val = read32(snvs + SNVS_LPCR);
+	val = io_read32(snvs + SNVS_LPCR);
 	val |= SNVS_LPCR_SRTC_ENV_MASK;
-	write32(val, snvs + SNVS_LPCR);
+	io_write32(snvs + SNVS_LPCR, val);
 
 	do {
-		val = read32(snvs + SNVS_LPCR);
+		val = io_read32(snvs + SNVS_LPCR);
 		if (val & SNVS_LPCR_SRTC_ENV_MASK)
 			break;
 	} while (--timeout);
diff --git a/core/drivers/imx_uart.c b/core/drivers/imx_uart.c
index ae06d0e0..115bd82a 100644
--- a/core/drivers/imx_uart.c
+++ b/core/drivers/imx_uart.c
@@ -93,8 +93,8 @@ static void imx_uart_flush(struct serial_chip *chip)
 	vaddr_t base = chip_to_base(chip);
 
 
-	while (!(read32(base + UTS) & UTS_TXEMPTY))
-		if (!(read32(base + UCR1) & UCR1_UARTEN))
+	while (!(io_read32(base + UTS) & UTS_TXEMPTY))
+		if (!(io_read32(base + UCR1) & UCR1_UARTEN))
 			return;
 }
 
@@ -102,10 +102,10 @@ static int imx_uart_getchar(struct serial_chip *chip)
 {
 	vaddr_t base = chip_to_base(chip);
 
-	while (read32(base + UTS) & UTS_RXEMPTY)
+	while (io_read32(base + UTS) & UTS_RXEMPTY)
 		;
 
-	return (read32(base + URXD) & URXD_RX_DATA);
+	return (io_read32(base + URXD) & URXD_RX_DATA);
 }
 
 static void imx_uart_putc(struct serial_chip *chip, int ch)
@@ -113,11 +113,11 @@ static void imx_uart_putc(struct serial_chip *chip, int ch)
 	vaddr_t base = chip_to_base(chip);
 
 	/* Wait until there's space in the TX FIFO */
-	while (read32(base + UTS) & UTS_TXFULL)
-		if (!(read32(base + UCR1) & UCR1_UARTEN))
+	while (io_read32(base + UTS) & UTS_TXFULL)
+		if (!(io_read32(base + UCR1) & UCR1_UARTEN))
 			return;
 
-	write32(ch, base + UTXD);
+	io_write32(base + UTXD, ch);
 }
 
 static const struct serial_ops imx_uart_ops = {
diff --git a/core/drivers/imx_wdog.c b/core/drivers/imx_wdog.c
index cc48f1b6..a6359b3d 100644
--- a/core/drivers/imx_wdog.c
+++ b/core/drivers/imx_wdog.c
@@ -60,16 +60,16 @@ void imx_wdog_restart(void)
 
 	DMSG("val %x\n", val);
 
-	write16(val, wdog_base + WDT_WCR);
+	io_write16(wdog_base + WDT_WCR, val);
 	dsb();
 
-	if (read16(wdog_base + WDT_WCR) & WDT_WCR_WDE) {
-		write16(WDT_SEQ1, wdog_base + WDT_WSR);
-		write16(WDT_SEQ2, wdog_base + WDT_WSR);
+	if (io_read16(wdog_base + WDT_WCR) & WDT_WCR_WDE) {
+		io_write16(wdog_base + WDT_WSR, WDT_SEQ1);
+		io_write16(wdog_base + WDT_WSR, WDT_SEQ2);
 	}
 
-	write16(val, wdog_base + WDT_WCR);
-	write16(val, wdog_base + WDT_WCR);
+	io_write16(wdog_base + WDT_WCR, val);
+	io_write16(wdog_base + WDT_WCR, val);
 
 	while (1)
 		;
diff --git a/core/drivers/mvebu_uart.c b/core/drivers/mvebu_uart.c
index cc70f02f..749a6e55 100644
--- a/core/drivers/mvebu_uart.c
+++ b/core/drivers/mvebu_uart.c
@@ -72,7 +72,7 @@ static void mvebu_uart_flush(struct serial_chip *chip)
 	 * enabled flag. Checking it in the loop makes the code safe against
 	 * asynchronous disable.
 	 */
-	while (!(read32(base + UART_STATUS_REG) & UARTLSR_TXFIFOEMPTY))
+	while (!(io_read32(base + UART_STATUS_REG) & UARTLSR_TXFIFOEMPTY))
 		;
 }
 
@@ -80,7 +80,7 @@ static bool mvebu_uart_have_rx_data(struct serial_chip *chip)
 {
 	vaddr_t base = chip_to_base(chip);
 
-	return (read32(base + UART_STATUS_REG) & UART_RX_READY);
+	return (io_read32(base + UART_STATUS_REG) & UART_RX_READY);
 }
 
 static int mvebu_uart_getchar(struct serial_chip *chip)
@@ -89,7 +89,7 @@ static int mvebu_uart_getchar(struct serial_chip *chip)
 
 	while (!mvebu_uart_have_rx_data(chip))
 		;
-	return read32(base + UART_RX_REG) & 0xff;
+	return io_read32(base + UART_RX_REG) & 0xff;
 }
 
 static void mvebu_uart_putc(struct serial_chip *chip, int ch)
@@ -99,11 +99,11 @@ static void mvebu_uart_putc(struct serial_chip *chip, int ch)
 	uint32_t tmp;
 	/* wait for space in tx FIFO */
 	do {
-		tmp = read32(base + UART_STATUS_REG);
+		tmp = io_read32(base + UART_STATUS_REG);
 		tmp &= UARTLSR_TXFIFOFULL;
 	} while (tmp == UARTLSR_TXFIFOFULL);
 
-	write32(ch, base + UART_TX_REG);
+	io_write32(base + UART_TX_REG, ch);
 }
 
 static const struct serial_ops mvebu_uart_ops = {
@@ -118,7 +118,6 @@ void mvebu_uart_init(struct mvebu_uart_data *pd, paddr_t pbase,
 		uint32_t uart_clk, uint32_t baud_rate)
 {
 	vaddr_t base;
-	uint32_t tmp = 0;
 	uint32_t dll = 0;
 
 	pd->base.pa = pbase;
@@ -129,20 +128,17 @@ void mvebu_uart_init(struct mvebu_uart_data *pd, paddr_t pbase,
 	dll = (uart_clk / (baud_rate << 4)) & 0x3FF;
 
 	/* init UART  */
-	tmp = read32(base + UART_BAUD_REG);
-	tmp &= ~0x3FF;
-	tmp |= dll;
-	write32(tmp, base + UART_BAUD_REG);   /* set baud rate divisor */
+	io_clrsetbits32(base + UART_BAUD_REG, 0x3FF, dll);
 
 	/* set UART to default 16x scheme */
-	write32(0, base + UART_POSSR_REG);
+	io_write32(base + UART_POSSR_REG, 0);
 
 	/* reset FIFO */
-	write32((UART_CTRL_RXFIFO_RESET | UART_CTRL_TXFIFO_RESET),
-		base + UART_CTRL_REG);
+	io_write32(base + UART_CTRL_REG,
+		   UART_CTRL_RXFIFO_RESET | UART_CTRL_TXFIFO_RESET);
 
 	/* No Parity, 1 stop */
-	write32(0, base + UART_CTRL_REG);
+	io_write32(base + UART_CTRL_REG, 0);
 
 	mvebu_uart_flush(&pd->chip);
 }
diff --git a/core/drivers/ns16550.c b/core/drivers/ns16550.c
index 0578fd85..4d4bb4fc 100644
--- a/core/drivers/ns16550.c
+++ b/core/drivers/ns16550.c
@@ -58,7 +58,7 @@ static void ns16550_flush(struct serial_chip *chip)
 {
 	vaddr_t base = chip_to_base(chip);
 
-	while ((read8(base + UART_LSR) & UART_LSR_THRE) == 0)
+	while ((io_read8(base + UART_LSR) & UART_LSR_THRE) == 0)
 		;
 }
 
@@ -69,7 +69,7 @@ static void ns16550_putc(struct serial_chip *chip, int ch)
 	ns16550_flush(chip);
 
 	/* write out charset to Transmit-hold-register */
-	write8(ch, base + UART_THR);
+	io_write8(base + UART_THR, ch);
 }
 
 static const struct serial_ops ns16550_ops = {
diff --git a/core/drivers/pl011.c b/core/drivers/pl011.c
index b5941d5f..e8c5528e 100644
--- a/core/drivers/pl011.c
+++ b/core/drivers/pl011.c
@@ -93,8 +93,8 @@ static void pl011_flush(struct serial_chip *chip)
 	 * enabled flag. Checking it in the loop makes the code safe against
 	 * asynchronous disable.
 	 */
-	while ((read32(base + UART_CR) & UART_CR_UARTEN) &&
-	       !(read32(base + UART_FR) & UART_FR_TXFE))
+	while ((io_read32(base + UART_CR) & UART_CR_UARTEN) &&
+	       !(io_read32(base + UART_FR) & UART_FR_TXFE))
 		;
 }
 
@@ -102,7 +102,7 @@ static bool pl011_have_rx_data(struct serial_chip *chip)
 {
 	vaddr_t base = chip_to_base(chip);
 
-	return !(read32(base + UART_FR) & UART_FR_RXFE);
+	return !(io_read32(base + UART_FR) & UART_FR_RXFE);
 }
 
 static int pl011_getchar(struct serial_chip *chip)
@@ -111,7 +111,7 @@ static int pl011_getchar(struct serial_chip *chip)
 
 	while (!pl011_have_rx_data(chip))
 		;
-	return read32(base + UART_DR) & 0xff;
+	return io_read32(base + UART_DR) & 0xff;
 }
 
 static void pl011_putc(struct serial_chip *chip, int ch)
@@ -119,11 +119,11 @@ static void pl011_putc(struct serial_chip *chip, int ch)
 	vaddr_t base = chip_to_base(chip);
 
 	/* Wait until there is space in the FIFO or device is disabled */
-	while (read32(base + UART_FR) & UART_FR_TXFF)
+	while (io_read32(base + UART_FR) & UART_FR_TXFF)
 		;
 
 	/* Send the character */
-	write32(ch, base + UART_DR);
+	io_write32(base + UART_DR, ch);
 }
 
 static const struct serial_ops pl011_ops = {
@@ -145,25 +145,25 @@ void pl011_init(struct pl011_data *pd, paddr_t pbase, uint32_t uart_clk,
 	base = io_pa_or_va(&pd->base);
 
 	/* Clear all errors */
-	write32(0, base + UART_RSR_ECR);
+	io_write32(base + UART_RSR_ECR, 0);
 	/* Disable everything */
-	write32(0, base + UART_CR);
+	io_write32(base + UART_CR, 0);
 
 	if (baud_rate) {
 		uint32_t divisor = (uart_clk * 4) / baud_rate;
 
-		write32(divisor >> 6, base + UART_IBRD);
-		write32(divisor & 0x3f, base + UART_FBRD);
+		io_write32(base + UART_IBRD, divisor >> 6);
+		io_write32(base + UART_FBRD, divisor & 0x3f);
 	}
 
 	/* Configure TX to 8 bits, 1 stop bit, no parity, fifo disabled. */
-	write32(UART_LCRH_WLEN_8, base + UART_LCR_H);
+	io_write32(base + UART_LCR_H, UART_LCRH_WLEN_8);
 
 	/* Enable interrupts for receive and receive timeout */
-	write32(UART_IMSC_RXIM | UART_IMSC_RTIM, base + UART_IMSC);
+	io_write32(base + UART_IMSC, UART_IMSC_RXIM | UART_IMSC_RTIM);
 
 	/* Enable UART and RX/TX */
-	write32(UART_CR_UARTEN | UART_CR_TXE | UART_CR_RXE, base + UART_CR);
+	io_write32(base + UART_CR, UART_CR_UARTEN | UART_CR_TXE | UART_CR_RXE);
 
 	pl011_flush(&pd->chip);
 }
diff --git a/core/drivers/pl022_spi.c b/core/drivers/pl022_spi.c
index c7d21060..c7fc992a 100644
--- a/core/drivers/pl022_spi.c
+++ b/core/drivers/pl022_spi.c
@@ -151,25 +151,25 @@ static enum spi_result pl022_txrx8(struct spi_chip *chip, uint8_t *wdat,
 
 	if (wdat)
 		while (i < num_pkts) {
-			if (read8(pd->base + SSPSR) & SSPSR_TNF) {
+			if (io_read8(pd->base + SSPSR) & SSPSR_TNF) {
 				/* tx 1 packet */
-				write8(wdat[i++], pd->base + SSPDR);
+				io_write8(pd->base + SSPDR, wdat[i++]);
 			}
 
 			if (rdat)
-				if (read8(pd->base + SSPSR) & SSPSR_RNE) {
+				if (io_read8(pd->base + SSPSR) & SSPSR_RNE) {
 					/* rx 1 packet */
-					rdat[j++] = read8(pd->base + SSPDR);
+					rdat[j++] = io_read8(pd->base + SSPDR);
 				}
 		}
 
 	/* Capture remaining rdat not read above */
 	if (rdat) {
 		while ((j < num_pkts) &&
-			(read8(pd->base + SSPSR) & SSPSR_BSY))
-			if (read8(pd->base + SSPSR) & SSPSR_RNE) {
+			(io_read8(pd->base + SSPSR) & SSPSR_BSY))
+			if (io_read8(pd->base + SSPSR) & SSPSR_RNE) {
 				/* rx 1 packet */
-				rdat[j++] = read8(pd->base + SSPDR);
+				rdat[j++] = io_read8(pd->base + SSPDR);
 			}
 
 		if (j < num_pkts) {
@@ -197,25 +197,25 @@ static enum spi_result pl022_txrx16(struct spi_chip *chip, uint16_t *wdat,
 
 	if (wdat)
 		while (i < num_pkts) {
-			if (read8(pd->base + SSPSR) & SSPSR_TNF) {
+			if (io_read8(pd->base + SSPSR) & SSPSR_TNF) {
 				/* tx 1 packet */
-				write16(wdat[i++], pd->base + SSPDR);
+				io_write16(pd->base + SSPDR, wdat[i++]);
 			}
 
 			if (rdat)
-				if (read8(pd->base + SSPSR) & SSPSR_RNE) {
+				if (io_read8(pd->base + SSPSR) & SSPSR_RNE) {
 					/* rx 1 packet */
-					rdat[j++] = read16(pd->base + SSPDR);
+					rdat[j++] = io_read8(pd->base + SSPDR);
 				}
 		}
 
 	/* Capture remaining rdat not read above */
 	if (rdat) {
 		while ((j < num_pkts) &&
-			(read8(pd->base + SSPSR) & SSPSR_BSY))
-			if (read8(pd->base + SSPSR) & SSPSR_RNE) {
+			(io_read8(pd->base + SSPSR) & SSPSR_BSY))
+			if (io_read8(pd->base + SSPSR) & SSPSR_RNE) {
 				/* rx 1 packet */
-				rdat[j++] = read16(pd->base + SSPDR);
+				rdat[j++] = io_read8(pd->base + SSPDR);
 			}
 
 		if (j < num_pkts) {
@@ -232,20 +232,20 @@ static void pl022_print_peri_id(struct pl022_data *pd __maybe_unused)
 {
 	DMSG("Expected: 0x 22 10 ?4 00");
 	DMSG("Read: 0x %02x %02x %02x %02x",
-		read32(pd->base + SSPPeriphID0),
-		read32(pd->base + SSPPeriphID1),
-		read32(pd->base + SSPPeriphID2),
-		read32(pd->base + SSPPeriphID3));
+		io_read8(pd->base + SSPPeriphID0),
+		io_read8(pd->base + SSPPeriphID1),
+		io_read8(pd->base + SSPPeriphID2),
+		io_read8(pd->base + SSPPeriphID3));
 }
 
 static void pl022_print_cell_id(struct pl022_data *pd __maybe_unused)
 {
 	DMSG("Expected: 0x 0d f0 05 b1");
 	DMSG("Read: 0x %02x %02x %02x %02x",
-		read32(pd->base + SSPPCellID0),
-		read32(pd->base + SSPPCellID1),
-		read32(pd->base + SSPPCellID2),
-		read32(pd->base + SSPPCellID3));
+		io_read8(pd->base + SSPPCellID0),
+		io_read8(pd->base + SSPPCellID1),
+		io_read8(pd->base + SSPPCellID2),
+		io_read8(pd->base + SSPPCellID3));
 }
 
 static void pl022_sanity_check(struct pl022_data *pd)
@@ -271,7 +271,7 @@ static void pl022_sanity_check(struct pl022_data *pd)
 
 	#ifdef PLATFORM_hikey
 	DMSG("SSPB2BTRANS: Expected: 0x2. Read: 0x%x",
-		read32(pd->base + SSPB2BTRANS));
+		io_read8(pd->base + SSPB2BTRANS));
 	#endif
 	pl022_print_peri_id(pd);
 	pl022_print_cell_id(pd);
@@ -289,9 +289,9 @@ static void pl022_control_cs(struct spi_chip *chip, enum gpio_level value)
 
 	switch (pd->cs_control) {
 	case PL022_CS_CTRL_AUTO_GPIO:
-		if (read8(pd->base + SSPSR) & SSPSR_BSY)
+		if (io_read8(pd->base + SSPSR) & SSPSR_BSY)
 			DMSG("pl022 busy - do NOT set CS!");
-		while (read8(pd->base + SSPSR) & SSPSR_BSY)
+		while (io_read8(pd->base + SSPSR) & SSPSR_BSY)
 			;
 		DMSG("pl022 done - set CS!");
 
@@ -359,11 +359,11 @@ static void pl022_flush_fifo(struct pl022_data *pd)
 	uint32_t __maybe_unused rdat;
 
 	do {
-		while (read32(pd->base + SSPSR) & SSPSR_RNE) {
-			rdat = read32(pd->base + SSPDR);
+		while (io_read32(pd->base + SSPSR) & SSPSR_RNE) {
+			rdat = io_read32(pd->base + SSPDR);
 			DMSG("rdat: 0x%x", rdat);
 		}
-	} while (read32(pd->base + SSPSR) & SSPSR_BSY);
+	} while (io_read32(pd->base + SSPSR) & SSPSR_BSY);
 }
 
 static void pl022_configure(struct spi_chip *chip)
diff --git a/core/drivers/pl061_gpio.c b/core/drivers/pl061_gpio.c
index a4bdb35b..95e9571a 100644
--- a/core/drivers/pl061_gpio.c
+++ b/core/drivers/pl061_gpio.c
@@ -49,7 +49,7 @@ static enum gpio_dir pl061_get_direction(unsigned int gpio_pin)
 
 	base_addr = pl061_reg_base[gpio_pin / GPIOS_PER_PL061];
 	offset = gpio_pin % GPIOS_PER_PL061;
-	data = read8(base_addr + GPIODIR);
+	data = io_read8(base_addr + GPIODIR);
 	if (data & BIT(offset))
 		return GPIO_DIR_OUT;
 	return GPIO_DIR_IN;
@@ -58,20 +58,16 @@ static enum gpio_dir pl061_get_direction(unsigned int gpio_pin)
 static void pl061_set_direction(unsigned int gpio_pin, enum gpio_dir direction)
 {
 	vaddr_t base_addr;
-	uint8_t data;
 	unsigned int offset;
 
 	assert(gpio_pin < PLAT_PL061_MAX_GPIOS);
 
 	base_addr = pl061_reg_base[gpio_pin / GPIOS_PER_PL061];
 	offset = gpio_pin % GPIOS_PER_PL061;
-	if (direction == GPIO_DIR_OUT) {
-		data = read8(base_addr + GPIODIR) | BIT(offset);
-		write8(data, base_addr + GPIODIR);
-	} else {
-		data = read8(base_addr + GPIODIR) & ~BIT(offset);
-		write8(data, base_addr + GPIODIR);
-	}
+	if (direction == GPIO_DIR_OUT)
+		io_setbits8(base_addr + GPIODIR, BIT(offset));
+	else
+		io_clrbits8(base_addr + GPIODIR, BIT(offset));
 }
 
 /*
@@ -91,7 +87,7 @@ static enum gpio_level pl061_get_value(unsigned int gpio_pin)
 
 	base_addr = pl061_reg_base[gpio_pin / GPIOS_PER_PL061];
 	offset = gpio_pin % GPIOS_PER_PL061;
-	if (read8(base_addr + BIT(offset + 2)))
+	if (io_read8(base_addr + BIT(offset + 2)))
 		return GPIO_LEVEL_HIGH;
 	return GPIO_LEVEL_LOW;
 }
@@ -111,9 +107,9 @@ static void pl061_set_value(unsigned int gpio_pin, enum gpio_level value)
 	base_addr = pl061_reg_base[gpio_pin / GPIOS_PER_PL061];
 	offset = gpio_pin % GPIOS_PER_PL061;
 	if (value == GPIO_LEVEL_HIGH)
-		write8(BIT(offset), base_addr + BIT(offset + 2));
+		io_write8(base_addr + BIT(offset + 2), BIT(offset));
 	else
-		write8(0, base_addr + BIT(offset + 2));
+		io_write8(base_addr + BIT(offset + 2), 0);
 }
 
 static enum gpio_interrupt pl061_get_interrupt(unsigned int gpio_pin)
@@ -126,7 +122,7 @@ static enum gpio_interrupt pl061_get_interrupt(unsigned int gpio_pin)
 
 	base_addr = pl061_reg_base[gpio_pin / GPIOS_PER_PL061];
 	offset = gpio_pin % GPIOS_PER_PL061;
-	data = read8(base_addr + GPIOIE);
+	data = io_read8(base_addr + GPIOIE);
 	if (data & BIT(offset))
 		return GPIO_INTERRUPT_ENABLE;
 	return GPIO_INTERRUPT_DISABLE;
@@ -136,20 +132,16 @@ static void pl061_set_interrupt(unsigned int gpio_pin,
 	enum gpio_interrupt ena_dis)
 {
 	vaddr_t base_addr;
-	uint8_t data;
 	unsigned int offset;
 
 	assert(gpio_pin < PLAT_PL061_MAX_GPIOS);
 
 	base_addr = pl061_reg_base[gpio_pin / GPIOS_PER_PL061];
 	offset = gpio_pin % GPIOS_PER_PL061;
-	if (ena_dis == GPIO_INTERRUPT_ENABLE) {
-		data = read8(base_addr + GPIOIE) | BIT(offset);
-		write8(data, base_addr + GPIOIE);
-	} else {
-		data = read8(base_addr + GPIOIE) & ~BIT(offset);
-		write8(data, base_addr + GPIOIE);
-	}
+	if (ena_dis == GPIO_INTERRUPT_ENABLE)
+		io_setbits8(base_addr + GPIOIE, BIT(offset));
+	else
+		io_clrbits8(base_addr + GPIOIE, BIT(offset));
 }
 
 /*
@@ -194,7 +186,7 @@ enum pl061_mode_control pl061_get_mode_control(unsigned int gpio_pin)
 
 	base_addr = pl061_reg_base[gpio_pin / GPIOS_PER_PL061];
 	offset = gpio_pin % GPIOS_PER_PL061;
-	data = read8(base_addr + GPIOAFSEL);
+	data = io_read8(base_addr + GPIOAFSEL);
 	if (data & BIT(offset))
 		return PL061_MC_HW;
 	return PL061_MC_SW;
@@ -204,18 +196,14 @@ void pl061_set_mode_control(unsigned int gpio_pin,
 	enum pl061_mode_control hw_sw)
 {
 	vaddr_t base_addr;
-	uint8_t data;
 	unsigned int offset;
 
 	assert(gpio_pin < PLAT_PL061_MAX_GPIOS);
 
 	base_addr = pl061_reg_base[gpio_pin / GPIOS_PER_PL061];
 	offset = gpio_pin % GPIOS_PER_PL061;
-	if (hw_sw == PL061_MC_HW) {
-		data = read8(base_addr + GPIOAFSEL) | BIT(offset);
-		write8(data, base_addr + GPIOAFSEL);
-	} else {
-		data = read8(base_addr + GPIOAFSEL) & ~BIT(offset);
-		write8(data, base_addr + GPIOAFSEL);
-	}
+	if (hw_sw == PL061_MC_HW)
+		io_setbits8(base_addr + GPIOAFSEL, BIT(offset));
+	else
+		io_clrbits8(base_addr + GPIOAFSEL, BIT(offset));
 }
diff --git a/core/drivers/scif.c b/core/drivers/scif.c
index 1d094564..ae3f0138 100644
--- a/core/drivers/scif.c
+++ b/core/drivers/scif.c
@@ -57,7 +57,7 @@ static void scif_uart_flush(struct serial_chip *chip)
 {
 	vaddr_t base = chip_to_base(chip);
 
-	while (!(read16(base + SCIF_SCFSR) & SCFSR_TEND))
+	while (!(io_read16(base + SCIF_SCFSR) & SCFSR_TEND))
 		;
 }
 
@@ -66,12 +66,11 @@ static void scif_uart_putc(struct serial_chip *chip, int ch)
 	vaddr_t base = chip_to_base(chip);
 
 	/* Wait until there is space in the FIFO */
-	while ((read16(base + SCIF_SCFDR) >> SCFDR_T_SHIFT) >=
+	while ((io_read16(base + SCIF_SCFDR) >> SCFDR_T_SHIFT) >=
 		SCIF_TX_FIFO_SIZE)
 		;
-	write8(ch, base + SCIF_SCFTDR);
-	write16(read16(base + SCIF_SCFSR) & ~(SCFSR_TEND | SCFSR_TDFE),
-		base + SCIF_SCFSR);
+	io_write8(base + SCIF_SCFTDR, ch);
+	io_clrbits16(base + SCIF_SCFSR, SCFSR_TEND | SCFSR_TDFE);
 }
 
 static const struct serial_ops scif_uart_ops = {
@@ -86,7 +85,7 @@ void scif_uart_init(struct scif_uart_data *pd, paddr_t base)
 	pd->chip.ops = &scif_uart_ops;
 
 	/* Set Transmit Enable in Control register */
-	write16(read16(base + SCIF_SCSCR) | SCSCR_TE, base + SCIF_SCSCR);
+	io_setbits16(base + SCIF_SCSCR, SCSCR_TE);
 
 	scif_uart_flush(&pd->chip);
 }
diff --git a/core/drivers/serial8250_uart.c b/core/drivers/serial8250_uart.c
index f3326148..9330a230 100644
--- a/core/drivers/serial8250_uart.c
+++ b/core/drivers/serial8250_uart.c
@@ -42,7 +42,7 @@ static void serial8250_uart_flush(struct serial_chip *chip)
 	vaddr_t base = chip_to_base(chip);
 
 	while (1) {
-		uint32_t state = read32(base + UART_LSR);
+		uint32_t state = io_read32(base + UART_LSR);
 
 		/* Wait until transmit FIFO is empty */
 		if ((state & LSR_EMPTY) == LSR_EMPTY)
@@ -54,7 +54,7 @@ static bool serial8250_uart_have_rx_data(struct serial_chip *chip)
 {
 	vaddr_t base = chip_to_base(chip);
 
-	return (read32(base + UART_LSR) & LSR_DR);
+	return (io_read32(base + UART_LSR) & LSR_DR);
 }
 
 static int serial8250_uart_getchar(struct serial_chip *chip)
@@ -65,7 +65,7 @@ static int serial8250_uart_getchar(struct serial_chip *chip)
 		/* Transmit FIFO is empty, waiting again */
 		;
 	}
-	return read32(base + UART_RHR) & 0xff;
+	return io_read32(base + UART_RHR) & 0xff;
 }
 
 static void serial8250_uart_putc(struct serial_chip *chip, int ch)
@@ -75,7 +75,7 @@ static void serial8250_uart_putc(struct serial_chip *chip, int ch)
 	serial8250_uart_flush(chip);
 
 	/* Write out character to transmit FIFO */
-	write32(ch, base + UART_THR);
+	io_write32(base + UART_THR, ch);
 }
 
 static const struct serial_ops serial8250_uart_ops = {
diff --git a/core/drivers/sprd_uart.c b/core/drivers/sprd_uart.c
index e7e11b1e..d94649b0 100644
--- a/core/drivers/sprd_uart.c
+++ b/core/drivers/sprd_uart.c
@@ -52,7 +52,7 @@ static void sprd_uart_flush(struct serial_chip *chip)
 {
 	vaddr_t base = chip_to_base(chip);
 
-	while (read32(base + UART_STS1) & STS1_TXF_CNT_MASK)
+	while (io_read32(base + UART_STS1) & STS1_TXF_CNT_MASK)
 		;
 }
 
@@ -60,7 +60,7 @@ static bool sprd_uart_have_rx_data(struct serial_chip *chip)
 {
 	vaddr_t base = chip_to_base(chip);
 
-	return !!(read32(base + UART_STS1) & STS1_RXF_CNT_MASK);
+	return !!(io_read32(base + UART_STS1) & STS1_RXF_CNT_MASK);
 }
 
 static void sprd_uart_putc(struct serial_chip *chip, int ch)
@@ -68,7 +68,7 @@ static void sprd_uart_putc(struct serial_chip *chip, int ch)
 	vaddr_t base = chip_to_base(chip);
 
 	sprd_uart_flush(chip);
-	write32(base + UART_TXD, ch);
+	io_write32(base + UART_TXD, ch);
 }
 
 static int sprd_uart_getchar(struct serial_chip *chip)
@@ -78,7 +78,7 @@ static int sprd_uart_getchar(struct serial_chip *chip)
 	while (!sprd_uart_have_rx_data(chip))
 		;
 
-	return read32(base + UART_RXD) & 0xff;
+	return io_read32(base + UART_RXD) & 0xff;
 }
 
 static const struct serial_ops sprd_uart_ops = {
diff --git a/core/drivers/stih_asc.c b/core/drivers/stih_asc.c
index c1a921f4..b3fc100b 100644
--- a/core/drivers/stih_asc.c
+++ b/core/drivers/stih_asc.c
@@ -26,7 +26,7 @@ static void stih_asc_flush(struct serial_chip *chip)
 {
 	vaddr_t base = chip_to_base(chip);
 
-	while (!(read32(base + ASC_STATUS) & ASC_STATUS_TX_EMPTY))
+	while (!(io_read32(base + ASC_STATUS) & ASC_STATUS_TX_EMPTY))
 		;
 }
 
@@ -34,10 +34,10 @@ static void stih_asc_putc(struct serial_chip *chip, int ch)
 {
 	vaddr_t base = chip_to_base(chip);
 
-	while (!(read32(base + ASC_STATUS) & ASC_STATUS_TX_HALF_EMPTY))
+	while (!(io_read32(base + ASC_STATUS) & ASC_STATUS_TX_HALF_EMPTY))
 		;
 
-	write32(ch, base + ASC_TXBUFFER);
+	io_write32(base + ASC_TXBUFFER, ch);
 }
 
 static const struct serial_ops stih_asc_ops = {
diff --git a/core/drivers/stm32_etzpc.c b/core/drivers/stm32_etzpc.c
index 5af3f363..c7b4b620 100644
--- a/core/drivers/stm32_etzpc.c
+++ b/core/drivers/stm32_etzpc.c
@@ -133,7 +133,7 @@ enum etzpc_decprot_attributes etzpc_get_decprot(uint32_t decprot_id)
 
 	assert(valid_decprot_id(decprot_id));
 
-	value = (read32(base + ETZPC_DECPROT0 + offset) >> shift) &
+	value = (io_read32(base + ETZPC_DECPROT0 + offset) >> shift) &
 		ETZPC_DECPROT0_MASK;
 
 	return (enum etzpc_decprot_attributes)value;
@@ -147,7 +147,7 @@ void etzpc_lock_decprot(uint32_t decprot_id)
 
 	assert(valid_decprot_id(decprot_id));
 
-	write32(mask, base + offset + ETZPC_DECPROT_LOCK0);
+	io_write32(base + offset + ETZPC_DECPROT_LOCK0, mask);
 
 	/* Save for PM */
 	etzpc_dev.periph_cfg[decprot_id] |= PERIPH_PM_LOCK_BIT;
@@ -161,7 +161,7 @@ bool etzpc_get_lock_decprot(uint32_t decprot_id)
 
 	assert(valid_decprot_id(decprot_id));
 
-	return read32(base + offset + ETZPC_DECPROT_LOCK0) & mask;
+	return io_read32(base + offset + ETZPC_DECPROT_LOCK0) & mask;
 }
 
 void etzpc_configure_tzma(uint32_t tzma_id, uint16_t tzma_value)
@@ -171,7 +171,7 @@ void etzpc_configure_tzma(uint32_t tzma_id, uint16_t tzma_value)
 
 	assert(valid_tzma_id(tzma_id));
 
-	write32(tzma_value, base + ETZPC_TZMA0_SIZE + offset);
+	io_write32(base + ETZPC_TZMA0_SIZE + offset, tzma_value);
 
 	/* Save for PM */
 	assert((tzma_value & ~TZMA_PM_VALUE_MASK) == 0);
@@ -186,7 +186,7 @@ uint16_t etzpc_get_tzma(uint32_t tzma_id)
 
 	assert(valid_tzma_id(tzma_id));
 
-	return read32(base + ETZPC_TZMA0_SIZE + offset);
+	return io_read32(base + ETZPC_TZMA0_SIZE + offset);
 }
 
 void etzpc_lock_tzma(uint32_t tzma_id)
@@ -209,7 +209,8 @@ bool etzpc_get_lock_tzma(uint32_t tzma_id)
 
 	assert(valid_tzma_id(tzma_id));
 
-	return read32(base + ETZPC_TZMA0_SIZE + offset) & ETZPC_TZMA0_SIZE_LOCK;
+	return io_read32(base + ETZPC_TZMA0_SIZE + offset) &
+	       ETZPC_TZMA0_SIZE_LOCK;
 }
 
 static TEE_Result etzpc_pm(enum pm_op op, unsigned int pm_hint __unused,
@@ -278,7 +279,7 @@ struct etzpc_hwcfg {
 
 static void get_hwcfg(struct etzpc_hwcfg *hwcfg)
 {
-	uint32_t reg = read32(etzpc_base() + ETZPC_HWCFGR);
+	uint32_t reg = io_read32(etzpc_base() + ETZPC_HWCFGR);
 
 	hwcfg->num_tzma = (reg & ETZPC_HWCFGR_NUM_TZMA_MASK) >>
 			  ETZPC_HWCFGR_NUM_TZMA_SHIFT;
@@ -306,7 +307,7 @@ static void init_devive_from_hw_config(struct etzpc_instance *dev,
 	dev->num_ahb_sec = hwcfg.num_ahb_sec;
 
 	DMSG("ETZPC revison 0x02%" PRIu8 ", per_sec %u, ahb_sec %u, tzma %u",
-	     read8(etzpc_base() + ETZPC_VERR),
+	     io_read8(etzpc_base() + ETZPC_VERR),
 	     hwcfg.num_per_sec, hwcfg.num_ahb_sec, hwcfg.num_tzma);
 
 	init_pm(dev);
diff --git a/core/drivers/stm32_gpio.c b/core/drivers/stm32_gpio.c
index ea4ab00b..da5c5f92 100644
--- a/core/drivers/stm32_gpio.c
+++ b/core/drivers/stm32_gpio.c
@@ -66,24 +66,24 @@ static void get_gpio_cfg(uint32_t bank, uint32_t pin, struct gpio_cfg *cfg)
 	 * 4bit fields are accessed at bit position being fourth the pin index
 	 * but accessed from 2 32bit registers at incremental addresses.
 	 */
-	cfg->mode = (read32(base + GPIO_MODER_OFFSET) >> (pin << 1)) &
+	cfg->mode = (io_read32(base + GPIO_MODER_OFFSET) >> (pin << 1)) &
 		     GPIO_MODE_MASK;
 
-	cfg->otype = (read32(base + GPIO_OTYPER_OFFSET) >> pin) & 1;
+	cfg->otype = (io_read32(base + GPIO_OTYPER_OFFSET) >> pin) & 1;
 
-	cfg->ospeed = (read32(base +  GPIO_OSPEEDR_OFFSET) >> (pin << 1)) &
+	cfg->ospeed = (io_read32(base +  GPIO_OSPEEDR_OFFSET) >> (pin << 1)) &
 		       GPIO_OSPEED_MASK;
 
-	cfg->pupd = (read32(base +  GPIO_PUPDR_OFFSET) >> (pin << 1)) &
+	cfg->pupd = (io_read32(base +  GPIO_PUPDR_OFFSET) >> (pin << 1)) &
 		     GPIO_PUPD_PULL_MASK;
 
-	cfg->od = (read32(base + GPIO_ODR_OFFSET) >> (pin << 1)) & 1;
+	cfg->od = (io_read32(base + GPIO_ODR_OFFSET) >> (pin << 1)) & 1;
 
 	if (pin < GPIO_ALT_LOWER_LIMIT)
-		cfg->af = (read32(base + GPIO_AFRL_OFFSET) >> (pin << 2)) &
+		cfg->af = (io_read32(base + GPIO_AFRL_OFFSET) >> (pin << 2)) &
 			   GPIO_ALTERNATE_MASK;
 	else
-		cfg->af = (read32(base + GPIO_AFRH_OFFSET) >>
+		cfg->af = (io_read32(base + GPIO_AFRH_OFFSET) >>
 			    ((pin - GPIO_ALT_LOWER_LIMIT) << 2)) &
 			   GPIO_ALTERNATE_MASK;
 
@@ -354,7 +354,7 @@ static __maybe_unused bool valid_gpio_config(unsigned int bank,
 					     unsigned int pin, bool input)
 {
 	vaddr_t base = stm32_get_gpio_bank_base(bank);
-	uint32_t mode = (read32(base + GPIO_MODER_OFFSET) >> (pin << 1)) &
+	uint32_t mode = (io_read32(base + GPIO_MODER_OFFSET) >> (pin << 1)) &
 			GPIO_MODE_MASK;
 
 	if (pin > GPIO_PIN_MAX)
@@ -376,7 +376,7 @@ int stm32_gpio_get_input_level(unsigned int bank, unsigned int pin)
 
 	stm32_clock_enable(clock);
 
-	if (read32(base + GPIO_IDR_OFFSET) == BIT(pin))
+	if (io_read32(base + GPIO_IDR_OFFSET) == BIT(pin))
 		rc = 1;
 
 	stm32_clock_disable(clock);
@@ -394,9 +394,9 @@ void stm32_gpio_set_output_level(unsigned int bank, unsigned int pin, int level)
 	stm32_clock_enable(clock);
 
 	if (level)
-		write32(BIT(pin), base + GPIO_BSRR_OFFSET);
+		io_write32(base + GPIO_BSRR_OFFSET, BIT(pin));
 	else
-		write32(BIT(pin + 16), base + GPIO_BSRR_OFFSET);
+		io_write32(base + GPIO_BSRR_OFFSET, BIT(pin + 16));
 
 	stm32_clock_disable(clock);
 }
diff --git a/core/drivers/stm32_uart.c b/core/drivers/stm32_uart.c
index 1ff00015..80beb0a9 100644
--- a/core/drivers/stm32_uart.c
+++ b/core/drivers/stm32_uart.c
@@ -55,7 +55,7 @@ static void loc_flush(struct serial_chip *chip)
 	vaddr_t base = loc_chip_to_base(chip);
 	uint64_t timeout = timeout_init_us(FLUSH_TIMEOUT_US);
 
-	while (!(read32(base + UART_REG_ISR) & USART_ISR_TXFE))
+	while (!(io_read32(base + UART_REG_ISR) & USART_ISR_TXFE))
 		if (timeout_elapsed(timeout))
 			return;
 }
@@ -65,18 +65,18 @@ static void loc_putc(struct serial_chip *chip, int ch)
 	vaddr_t base = loc_chip_to_base(chip);
 	uint64_t timeout = timeout_init_us(PUTC_TIMEOUT_US);
 
-	while (!(read32(base + UART_REG_ISR) & USART_ISR_TXE_TXFNF))
+	while (!(io_read32(base + UART_REG_ISR) & USART_ISR_TXE_TXFNF))
 		if (timeout_elapsed(timeout))
 			return;
 
-	write32(ch, base + UART_REG_TDR);
+	io_write32(base + UART_REG_TDR, ch);
 }
 
 static bool loc_have_rx_data(struct serial_chip *chip)
 {
 	vaddr_t base = loc_chip_to_base(chip);
 
-	return read32(base + UART_REG_ISR) & USART_ISR_RXNE_RXFNE;
+	return io_read32(base + UART_REG_ISR) & USART_ISR_RXNE_RXFNE;
 }
 
 static int loc_getchar(struct serial_chip *chip)
@@ -86,7 +86,7 @@ static int loc_getchar(struct serial_chip *chip)
 	while (!loc_have_rx_data(chip))
 		;
 
-	return read32(base + UART_REG_RDR) & 0xff;
+	return io_read32(base + UART_REG_RDR) & 0xff;
 }
 
 static const struct serial_ops stm32_uart_serial_ops = {
diff --git a/core/drivers/tzc380.c b/core/drivers/tzc380.c
index e4047fca..d1947a08 100644
--- a/core/drivers/tzc380.c
+++ b/core/drivers/tzc380.c
@@ -54,35 +54,35 @@ static struct tzc_instance tzc;
 
 static uint32_t tzc_read_build_config(vaddr_t base)
 {
-	return read32(base + BUILD_CONFIG_OFF);
+	return io_read32(base + BUILD_CONFIG_OFF);
 }
 
 static void tzc_write_action(vaddr_t base, enum tzc_action action)
 {
-	write32(action, base + ACTION_OFF);
+	io_write32(base + ACTION_OFF, action);
 }
 
 static void tzc_write_region_base_low(vaddr_t base, uint32_t region,
 				      uint32_t val)
 {
-	write32(val, base + REGION_SETUP_LOW_OFF(region));
+	io_write32(base + REGION_SETUP_LOW_OFF(region), val);
 }
 
 static void tzc_write_region_base_high(vaddr_t base, uint32_t region,
 				       uint32_t val)
 {
-	write32(val, base + REGION_SETUP_HIGH_OFF(region));
+	io_write32(base + REGION_SETUP_HIGH_OFF(region), val);
 }
 
 static uint32_t tzc_read_region_attributes(vaddr_t base, uint32_t region)
 {
-	return read32(base + REGION_ATTRIBUTES_OFF(region));
+	return io_read32(base + REGION_ATTRIBUTES_OFF(region));
 }
 
 static void tzc_write_region_attributes(vaddr_t base, uint32_t region,
 					uint32_t val)
 {
-	write32(val, base + REGION_ATTRIBUTES_OFF(region));
+	io_write32(base + REGION_ATTRIBUTES_OFF(region), val);
 }
 
 void tzc_init(vaddr_t base)
@@ -108,7 +108,7 @@ void tzc_init(vaddr_t base)
  */
 void tzc_security_inversion_en(vaddr_t base)
 {
-	write32(1, base + SECURITY_INV_EN_OFF);
+	io_write32(base + SECURITY_INV_EN_OFF, 1);
 }
 
 /*
@@ -137,18 +137,18 @@ void tzc_fail_dump(void)
 						      MEM_AREA_IO_SEC);
 
 	EMSG("Fail address Low 0x%" PRIx32,
-	     read32(base + FAIL_ADDRESS_LOW_OFF));
+	     io_read32(base + FAIL_ADDRESS_LOW_OFF));
 	EMSG("Fail address High 0x%" PRIx32,
-	     read32(base + FAIL_ADDRESS_HIGH_OFF));
-	EMSG("Fail Control 0x%" PRIx32, read32(base + FAIL_CONTROL_OFF));
-	EMSG("Fail Id 0x%" PRIx32, read32(base + FAIL_ID));
+	     io_read32(base + FAIL_ADDRESS_HIGH_OFF));
+	EMSG("Fail Control 0x%" PRIx32, io_read32(base + FAIL_CONTROL_OFF));
+	EMSG("Fail Id 0x%" PRIx32, io_read32(base + FAIL_ID));
 }
 
 void tzc_int_clear(void)
 {
 	vaddr_t base = core_mmu_get_va(tzc.base, MEM_AREA_IO_SEC);
 
-	write32(0, base + INT_CLEAR);
+	io_write32(base + INT_CLEAR, 0);
 }
 
 static uint32_t addr_low(vaddr_t addr)
@@ -208,12 +208,12 @@ void tzc_set_action(enum tzc_action action)
 
 static uint32_t tzc_read_region_base_low(vaddr_t base, uint32_t region)
 {
-	return read32(base + REGION_SETUP_LOW_OFF(region));
+	return io_read32(base + REGION_SETUP_LOW_OFF(region));
 }
 
 static uint32_t tzc_read_region_base_high(vaddr_t base, uint32_t region)
 {
-	return read32(base + REGION_SETUP_HIGH_OFF(region));
+	return io_read32(base + REGION_SETUP_HIGH_OFF(region));
 }
 
 #define	REGION_MAX	16
@@ -224,7 +224,7 @@ void tzc_dump_state(void)
 
 	DMSG("enter");
 	DMSG("security_inversion_en %x\n",
-	     read32(tzc.base + SECURITY_INV_EN_OFF));
+	     io_read32(tzc.base + SECURITY_INV_EN_OFF));
 	for (n = 0; n <= REGION_MAX; n++) {
 		temp_32reg = tzc_read_region_attributes(tzc.base, n);
 		if (!(temp_32reg & TZC_ATTR_REGION_EN_MASK))
diff --git a/core/drivers/tzc400.c b/core/drivers/tzc400.c
index 370fdb12..ff8a7a2a 100644
--- a/core/drivers/tzc400.c
+++ b/core/drivers/tzc400.c
@@ -81,74 +81,68 @@ static struct tzc_instance tzc;
 
 static uint32_t tzc_read_build_config(vaddr_t base)
 {
-	return read32(base + BUILD_CONFIG_OFF);
+	return io_read32(base + BUILD_CONFIG_OFF);
 }
 
 static uint32_t tzc_read_gate_keeper(vaddr_t base)
 {
-	return read32(base + GATE_KEEPER_OFF);
+	return io_read32(base + GATE_KEEPER_OFF);
 }
 
 static void tzc_write_gate_keeper(vaddr_t base, uint32_t val)
 {
-	write32(val, base + GATE_KEEPER_OFF);
+	io_write32(base + GATE_KEEPER_OFF, val);
 }
 
 static void tzc_write_action(vaddr_t base, enum tzc_action action)
 {
-	write32(action, base + ACTION_OFF);
+	io_write32(base + ACTION_OFF, action);
 }
 
 static void tzc_write_region_base_low(vaddr_t base, uint32_t region,
 				      uint32_t val)
 {
-	write32(val, base + REGION_BASE_LOW_OFF +
-		REGION_NUM_OFF(region));
+	io_write32(base + REGION_BASE_LOW_OFF + REGION_NUM_OFF(region), val);
 }
 
 static void tzc_write_region_base_high(vaddr_t base, uint32_t region,
 				       uint32_t val)
 {
-	write32(val, base + REGION_BASE_HIGH_OFF +
-		REGION_NUM_OFF(region));
+	io_write32(base + REGION_BASE_HIGH_OFF + REGION_NUM_OFF(region), val);
 }
 
 static void tzc_write_region_top_low(vaddr_t base, uint32_t region,
 				     uint32_t val)
 {
-	write32(val, base + REGION_TOP_LOW_OFF +
-		REGION_NUM_OFF(region));
+	io_write32(base + REGION_TOP_LOW_OFF + REGION_NUM_OFF(region), val);
 }
 
 static void tzc_write_region_top_high(vaddr_t base, uint32_t region,
 				      uint32_t val)
 {
-	write32(val, base + REGION_TOP_HIGH_OFF +
-		REGION_NUM_OFF(region));
+	io_write32(base + REGION_TOP_HIGH_OFF +	REGION_NUM_OFF(region), val);
 }
 
 static void tzc_write_region_attributes(vaddr_t base, uint32_t region,
 					uint32_t val)
 {
-	write32(val, base + REGION_ATTRIBUTES_OFF +
-		REGION_NUM_OFF(region));
+	io_write32(base + REGION_ATTRIBUTES_OFF + REGION_NUM_OFF(region), val);
 }
 
 static void tzc_write_region_id_access(vaddr_t base, uint32_t region,
 				       uint32_t val)
 {
-	write32(val, base + REGION_ID_ACCESS_OFF +
-		REGION_NUM_OFF(region));
+	io_write32(base + REGION_ID_ACCESS_OFF + REGION_NUM_OFF(region), val);
 }
 
 static uint32_t tzc_read_component_id(vaddr_t base)
 {
 	uint32_t id;
 
-	id = read8(base + CID0_OFF);
-	id |= SHIFT_U32(read8(base + CID1_OFF), 8);
-	id |= SHIFT_U32(read8(base + CID2_OFF), 16);
-	id |= SHIFT_U32(read8(base + CID3_OFF), 24);
+	id = io_read8(base + CID0_OFF);
+	id |= SHIFT_U32(io_read8(base + CID1_OFF), 8);
+	id |= SHIFT_U32(io_read8(base + CID2_OFF), 16);
+	id |= SHIFT_U32(io_read8(base + CID3_OFF), 24);
 
 	return id;
 }
@@ -350,27 +344,27 @@ void tzc_disable_filters(void)
 
 static uint32_t tzc_read_region_attributes(vaddr_t base, uint32_t region)
 {
-	return read32(base + REGION_ATTRIBUTES_OFF + REGION_NUM_OFF(region));
+	return io_read32(base + REGION_ATTRIBUTES_OFF + REGION_NUM_OFF(region));
 }
 
 static uint32_t tzc_read_region_base_low(vaddr_t base, uint32_t region)
 {
-	return read32(base + REGION_BASE_LOW_OFF + REGION_NUM_OFF(region));
+	return io_read32(base + REGION_BASE_LOW_OFF + REGION_NUM_OFF(region));
 }
 
 static uint32_t tzc_read_region_base_high(vaddr_t base, uint32_t region)
 {
-	return read32(base + REGION_BASE_HIGH_OFF + REGION_NUM_OFF(region));
+	return io_read32(base + REGION_BASE_HIGH_OFF + REGION_NUM_OFF(region));
 }
 
 static uint32_t tzc_read_region_top_low(vaddr_t base, uint32_t region)
 {
-	return read32(base + REGION_TOP_LOW_OFF + REGION_NUM_OFF(region));
+	return io_read32(base + REGION_TOP_LOW_OFF + REGION_NUM_OFF(region));
 }
 
 static uint32_t tzc_read_region_top_high(vaddr_t base, uint32_t region)
 {
-	return read32(base + REGION_TOP_HIGH_OFF + REGION_NUM_OFF(region));
+	return io_read32(base + REGION_TOP_HIGH_OFF + REGION_NUM_OFF(region));
 }
 
 #define	REGION_MAX		8