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| author | David Wang <david.wang@arm.com> | 2017-05-03 14:26:34 +0800 |
|---|---|---|
| committer | Jerome Forissier <jerome.forissier@linaro.org> | 2017-05-04 13:36:41 +0200 |
| commit | 440e2223a41dd8637dff463e143f2187f8616b7a (patch) | |
| tree | b2332d146180a6a5cfc4fb4142cc3d1b0a942c46 | |
| parent | e040af6cc36a9ae8587a4c718075ff84369749e3 (diff) | |
The other bits in GICD_CTLR should not be touched
The gic_init() function enables secure and non-secure group1
interrupts in GICD_CTLR register. But the other bits should
not be modified to avoid `UNPREDICTABLE` behaviours as per ARM
GICv3 specification.
Signed-off-by: David Wang <david.wang@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
[jf: minor edits to commit message]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
| -rw-r--r-- | core/drivers/gic.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/core/drivers/gic.c b/core/drivers/gic.c index a202eabc..cc2655dd 100644 --- a/core/drivers/gic.c +++ b/core/drivers/gic.c @@ -219,8 +219,8 @@ void gic_init(struct gic_data *gd, vaddr_t gicc_base __maybe_unused, write32(GICC_CTLR_ENABLEGRP0 | GICC_CTLR_ENABLEGRP1 | GICC_CTLR_FIQEN, gd->gicc_base + GICC_CTLR); #endif - write32(GICD_CTLR_ENABLEGRP0 | GICD_CTLR_ENABLEGRP1, - gd->gicd_base + GICD_CTLR); + write32(read32(gd->gicd_base + GICD_CTLR) | GICD_CTLR_ENABLEGRP0 | + GICD_CTLR_ENABLEGRP1, gd->gicd_base + GICD_CTLR); } void gic_init_base_addr(struct gic_data *gd, vaddr_t gicc_base __maybe_unused, |