diff options
| author | Sandeep Tripathy <sandeep.tripathy@broadcom.com> | 2019-02-19 15:41:45 +0530 |
|---|---|---|
| committer | Jérôme Forissier <jerome.forissier@linaro.org> | 2019-02-22 10:00:17 +0100 |
| commit | 1fcac774a84f3025789ea052d8f3d96a751d5ce4 (patch) | |
| tree | 42453a0486f10f8998717617d88c4d46e5c34749 | |
| parent | b7667020c9146b9dc760174406a42ab62b167f6b (diff) | |
drivers: GICv3: Configure native secure interrupt
OP-TEE dispatcher registers with TF-A to handle EL1S interrupts
by design. OP-TEE should own the G1S interrupts in GICv3.
-gic_it_add() should result in configuring a given interrupt to
G1S instead of G0 for GICv3.
-G1S interrupts to be enabled at distributor interface.
-system interface register ICC_IGRPEN1_EL1 to be used to enable
G1S interrupts.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
Reviewed-by: Soby Mathew <soby.mathew@arm.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
| -rw-r--r-- | core/arch/arm/include/arm64.h | 2 | ||||
| -rw-r--r-- | core/drivers/gic.c | 15 |
2 files changed, 12 insertions, 5 deletions
diff --git a/core/arch/arm/include/arm64.h b/core/arch/arm/include/arm64.h index b29677e2..8fc30214 100644 --- a/core/arch/arm/include/arm64.h +++ b/core/arch/arm/include/arm64.h @@ -334,6 +334,8 @@ DEFINE_REG_READ_FUNC_(icc_iar0, uint32_t, S3_0_c12_c8_0) DEFINE_REG_READ_FUNC_(icc_iar1, uint32_t, S3_0_c12_c12_0) DEFINE_REG_WRITE_FUNC_(icc_eoir0, uint32_t, S3_0_c12_c8_1) DEFINE_REG_WRITE_FUNC_(icc_eoir1, uint32_t, S3_0_c12_c12_1) +DEFINE_REG_WRITE_FUNC_(icc_igrpen0, uint32_t, S3_0_C12_C12_6) +DEFINE_REG_WRITE_FUNC_(icc_igrpen1, uint32_t, S3_0_C12_C12_7) #endif /*ASM*/ #endif /*ARM64_H*/ diff --git a/core/drivers/gic.c b/core/drivers/gic.c index 9735ae53..843a3090 100644 --- a/core/drivers/gic.c +++ b/core/drivers/gic.c @@ -22,6 +22,7 @@ #define GICC_CTLR_ENABLEGRP0 (1 << 0) #define GICC_CTLR_ENABLEGRP1 (1 << 1) +#define GICD_CTLR_ENABLEGRP1S (1 << 2) #define GICC_CTLR_FIQEN (1 << 3) /* Offsets from gic.gicd_base */ @@ -34,6 +35,7 @@ #define GICD_ICPENDR(n) (0x280 + (n) * 4) #define GICD_IPRIORITYR(n) (0x400 + (n) * 4) #define GICD_ITARGETSR(n) (0x800 + (n) * 4) +#define GICD_IGROUPMODR(n) (0xd00 + (n) * 4) #define GICD_SGIR (0xF00) #define GICD_CTLR_ENABLEGRP0 (1 << 0) @@ -147,8 +149,7 @@ void gic_cpu_init(struct gic_data *gd) */ #if defined(CFG_ARM_GICV3) write_icc_pmr(0x80); - write_icc_ctlr(GICC_CTLR_ENABLEGRP0 | GICC_CTLR_ENABLEGRP1 | - GICC_CTLR_FIQEN); + write_icc_igrpen1(1); #else io_write32(gd->gicc_base + GICC_PMR, 0x80); @@ -191,17 +192,17 @@ void gic_init(struct gic_data *gd, vaddr_t gicc_base __maybe_unused, */ #if defined(CFG_ARM_GICV3) write_icc_pmr(0x80); - write_icc_ctlr(GICC_CTLR_ENABLEGRP0 | GICC_CTLR_ENABLEGRP1 | - GICC_CTLR_FIQEN); + write_icc_igrpen1(1); + io_setbits32(gd->gicd_base + GICD_CTLR, GICD_CTLR_ENABLEGRP1S); #else io_write32(gd->gicc_base + GICC_PMR, 0x80); /* Enable GIC */ io_write32(gd->gicc_base + GICC_CTLR, GICC_CTLR_FIQEN | GICC_CTLR_ENABLEGRP0 | GICC_CTLR_ENABLEGRP1); -#endif io_setbits32(gd->gicd_base + GICD_CTLR, GICD_CTLR_ENABLEGRP0 | GICD_CTLR_ENABLEGRP1); +#endif } void gic_init_base_addr(struct gic_data *gd, vaddr_t gicc_base __maybe_unused, @@ -224,6 +225,10 @@ static void gic_it_add(struct gic_data *gd, size_t it) io_write32(gd->gicd_base + GICD_ICPENDR(idx), mask); /* Assign it to group0 */ io_clrbits32(gd->gicd_base + GICD_IGROUPR(idx), mask); +#if defined(CFG_ARM_GICV3) + /* Assign it to group1S */ + io_setbits32(gd->gicd_base + GICD_IGROUPMODR(idx), mask); +#endif } static void gic_it_set_cpu_mask(struct gic_data *gd, size_t it, |