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authorSumit Garg <sumit.garg@linaro.org>2018-10-04 18:10:01 +0530
committerJérôme Forissier <jerome.forissier@linaro.org>2018-11-12 13:56:10 +0100
commit1de462e11d33c7d52bfc6c583f467db3d2386d3d (patch)
tree3e674107923fd264d2d97c0c6f744611773051b1
parent74a41cfac8c066718b8d36f3de448d2c23180ef2 (diff)
drivers: GICv3: Handle group 1 secure interrupts
As per GICv3 architecture specification (Section 4.6 Interrupt grouping), secure EL1 (Trusted OS) handles secure group 1 physical interrupts and EL3 handles group 0 physical interrupts which are considered as FIQs (foreign interrupt) for Trusted OS. Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (FVP) Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
-rw-r--r--core/arch/arm/include/arm64.h2
-rw-r--r--core/drivers/gic.c4
2 files changed, 4 insertions, 2 deletions
diff --git a/core/arch/arm/include/arm64.h b/core/arch/arm/include/arm64.h
index a316e193..2c1fd8c2 100644
--- a/core/arch/arm/include/arm64.h
+++ b/core/arch/arm/include/arm64.h
@@ -327,7 +327,9 @@ DEFINE_REG_READ_FUNC_(icc_ctlr, uint32_t, S3_0_C12_C12_4)
DEFINE_REG_WRITE_FUNC_(icc_ctlr, uint32_t, S3_0_C12_C12_4)
DEFINE_REG_WRITE_FUNC_(icc_pmr, uint32_t, S3_0_C4_C6_0)
DEFINE_REG_READ_FUNC_(icc_iar0, uint32_t, S3_0_c12_c8_0)
+DEFINE_REG_READ_FUNC_(icc_iar1, uint32_t, S3_0_c12_c12_0)
DEFINE_REG_WRITE_FUNC_(icc_eoir0, uint32_t, S3_0_c12_c8_1)
+DEFINE_REG_WRITE_FUNC_(icc_eoir1, uint32_t, S3_0_c12_c12_1)
#endif /*ASM*/
#endif /*ARM64_H*/
diff --git a/core/drivers/gic.c b/core/drivers/gic.c
index 9baffee4..ab335a63 100644
--- a/core/drivers/gic.c
+++ b/core/drivers/gic.c
@@ -328,7 +328,7 @@ static void gic_it_raise_sgi(struct gic_data *gd, size_t it,
static uint32_t gic_read_iar(struct gic_data *gd __maybe_unused)
{
#if defined(CFG_ARM_GICV3)
- return read_icc_iar0();
+ return read_icc_iar1();
#else
return read32(gd->gicc_base + GICC_IAR);
#endif
@@ -337,7 +337,7 @@ static uint32_t gic_read_iar(struct gic_data *gd __maybe_unused)
static void gic_write_eoir(struct gic_data *gd __maybe_unused, uint32_t eoir)
{
#if defined(CFG_ARM_GICV3)
- write_icc_eoir0(eoir);
+ write_icc_eoir1(eoir);
#else
write32(eoir, gd->gicc_base + GICC_EOIR);
#endif