diff options
| author | Shiva Chen <shiva0217@gmail.com> | 2018-05-09 02:42:00 +0000 |
|---|---|---|
| committer | Shiva Chen <shiva0217@gmail.com> | 2018-05-09 02:42:00 +0000 |
| commit | 24abe71d71a06ca620830a43e348fdfdd518276c (patch) | |
| tree | e824a927c43e47e8a1193329949958df0b436942 | |
| parent | 085342284ca9c82dfe418063e1eb96b3aa93c429 (diff) | |
[DebugInfo] Examine all uses of isDebugValue() for debug instructions.
Because we create a new kind of debug instruction, DBG_LABEL, we need to
check all passes which use isDebugValue() to check MachineInstr is debug
instruction or not. When expelling debug instructions, we should expel
both DBG_VALUE and DBG_LABEL. So, I create a new function,
isDebugInstr(), in MachineInstr to check whether the MachineInstr is
debug instruction or not.
This patch has no new test case. I have run regression test and there is
no difference in regression test.
Differential Revision: https://reviews.llvm.org/D45342
Patch by Hsiangkai Wang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331844 91177308-0d34-0410-b5e6-96231b3b80d8
106 files changed, 233 insertions, 217 deletions
diff --git a/include/llvm/CodeGen/MachineBasicBlock.h b/include/llvm/CodeGen/MachineBasicBlock.h index 69c9e82ba92..c5241c0793f 100644 --- a/include/llvm/CodeGen/MachineBasicBlock.h +++ b/include/llvm/CodeGen/MachineBasicBlock.h @@ -700,7 +700,7 @@ public: bool IsCond); /// Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE - /// instructions. Return UnknownLoc if there is none. + /// and DBG_LABEL instructions. Return UnknownLoc if there is none. DebugLoc findDebugLoc(instr_iterator MBBI); DebugLoc findDebugLoc(iterator MBBI) { return findDebugLoc(MBBI.getInstrIterator()); @@ -897,7 +897,7 @@ public: /// const_instr_iterator} and the respective reverse iterators. template<typename IterT> inline IterT skipDebugInstructionsForward(IterT It, IterT End) { - while (It != End && It->isDebugValue()) + while (It != End && It->isDebugInstr()) It++; return It; } @@ -908,7 +908,7 @@ inline IterT skipDebugInstructionsForward(IterT It, IterT End) { /// const_instr_iterator} and the respective reverse iterators. template<class IterT> inline IterT skipDebugInstructionsBackward(IterT It, IterT Begin) { - while (It != Begin && It->isDebugValue()) + while (It != Begin && It->isDebugInstr()) It--; return It; } diff --git a/include/llvm/CodeGen/MachineInstrBuilder.h b/include/llvm/CodeGen/MachineInstrBuilder.h index 2df89b15dd5..d507c558f41 100644 --- a/include/llvm/CodeGen/MachineInstrBuilder.h +++ b/include/llvm/CodeGen/MachineInstrBuilder.h @@ -220,6 +220,9 @@ public: assert((MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable()) : true) && "first MDNode argument of a DBG_VALUE not a variable"); + assert((MI->isDebugLabel() ? static_cast<bool>(MI->getDebugLabel()) + : true) && + "first MDNode argument of a DBG_LABEL not a label"); return *this; } diff --git a/include/llvm/CodeGen/SlotIndexes.h b/include/llvm/CodeGen/SlotIndexes.h index e3e0e1cf0a5..334267d9828 100644 --- a/include/llvm/CodeGen/SlotIndexes.h +++ b/include/llvm/CodeGen/SlotIndexes.h @@ -578,9 +578,9 @@ class raw_ostream; assert(!MI.isInsideBundle() && "Instructions inside bundles should use bundle start's slot."); assert(mi2iMap.find(&MI) == mi2iMap.end() && "Instr already indexed."); - // Numbering DBG_VALUE instructions could cause code generation to be + // Numbering debug instructions could cause code generation to be // affected by debug information. - assert(!MI.isDebugValue() && "Cannot number DBG_VALUE instructions."); + assert(!MI.isDebugInstr() && "Cannot number debug instructions."); assert(MI.getParent() != nullptr && "Instr must be added to function."); diff --git a/lib/CodeGen/AggressiveAntiDepBreaker.cpp b/lib/CodeGen/AggressiveAntiDepBreaker.cpp index 1546f4f62f1..1f76bdda079 100644 --- a/lib/CodeGen/AggressiveAntiDepBreaker.cpp +++ b/lib/CodeGen/AggressiveAntiDepBreaker.cpp @@ -808,7 +808,7 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies( I != E; --Count) { MachineInstr &MI = *--I; - if (MI.isDebugValue()) + if (MI.isDebugInstr()) continue; DEBUG(dbgs() << "Anti: "); diff --git a/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/lib/CodeGen/AsmPrinter/AsmPrinter.cpp index 89e047a24f6..7fde84b254b 100644 --- a/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -1059,7 +1059,7 @@ void AsmPrinter::EmitFunctionBody() { for (auto &MI : MBB) { // Print the assembly for the instruction. if (!MI.isPosition() && !MI.isImplicitDef() && !MI.isKill() && - !MI.isDebugValue()) { + !MI.isDebugInstr()) { HasAnyRealCode = true; ++NumInstsInFunction; } diff --git a/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp b/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp index a7bc8a84818..0af3d1521eb 100644 --- a/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp +++ b/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp @@ -2589,8 +2589,8 @@ void CodeViewDebug::endFunctionImpl(const MachineFunction *MF) { void CodeViewDebug::beginInstruction(const MachineInstr *MI) { DebugHandlerBase::beginInstruction(MI); - // Ignore DBG_VALUE locations and function prologue. - if (!Asm || !CurFn || MI->isDebugValue() || + // Ignore DBG_VALUE and DBG_LABEL locations and function prologue. + if (!Asm || !CurFn || MI->isDebugInstr() || MI->getFlag(MachineInstr::FrameSetup)) return; @@ -2599,7 +2599,7 @@ void CodeViewDebug::beginInstruction(const MachineInstr *MI) { DebugLoc DL = MI->getDebugLoc(); if (!DL && MI->getParent() != PrevInstBB) { for (const auto &NextMI : *MI->getParent()) { - if (NextMI.isDebugValue()) + if (NextMI.isDebugInstr()) continue; DL = NextMI.getDebugLoc(); if (DL) diff --git a/lib/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp b/lib/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp index c6c661dddf9..daa045939ce 100644 --- a/lib/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp +++ b/lib/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp @@ -198,7 +198,7 @@ void llvm::calculateDbgValueHistory(const MachineFunction *MF, RegDescribedVarsMap RegVars; for (const auto &MBB : *MF) { for (const auto &MI : MBB) { - if (!MI.isDebugValue()) { + if (!MI.isDebugInstr()) { // Not a DBG_VALUE instruction. It may clobber registers which describe // some variables. for (const MachineOperand &MO : MI.operands()) { @@ -234,6 +234,10 @@ void llvm::calculateDbgValueHistory(const MachineFunction *MF, continue; } + // Skip DBG_LABEL instructions. + if (MI.isDebugLabel()) + continue; + assert(MI.getNumOperands() > 1 && "Invalid DBG_VALUE instruction!"); // Use the base variable (without any DW_OP_piece expressions) // as index into History. The full variables including the diff --git a/lib/CodeGen/BranchFolding.cpp b/lib/CodeGen/BranchFolding.cpp index d1dd7430f86..8db71130588 100644 --- a/lib/CodeGen/BranchFolding.cpp +++ b/lib/CodeGen/BranchFolding.cpp @@ -358,7 +358,7 @@ static unsigned ComputeCommonTailLength(MachineBasicBlock *MBB1, // I1==MBB1->begin() work as expected.) if (I1 == MBB1->begin() && I2 != MBB2->begin()) { --I2; - while (I2->isDebugValue()) { + while (I2->isDebugInstr()) { if (I2 == MBB2->begin()) return TailLen; --I2; @@ -367,7 +367,7 @@ static unsigned ComputeCommonTailLength(MachineBasicBlock *MBB1, } if (I2 == MBB2->begin() && I1 != MBB1->begin()) { --I1; - while (I1->isDebugValue()) { + while (I1->isDebugInstr()) { if (I1 == MBB1->begin()) return TailLen; --I1; @@ -1499,7 +1499,7 @@ ReoptimizeBlock: // Check if DBG_VALUE at the end of PrevBB is identical to the // DBG_VALUE at the beginning of MBB. while (PrevBBIter != PrevBB.begin() && MBBIter != MBB->end() - && PrevBBIter->isDebugValue() && MBBIter->isDebugValue()) { + && PrevBBIter->isDebugInstr() && MBBIter->isDebugInstr()) { if (!MBBIter->isIdenticalTo(*PrevBBIter)) break; MachineInstr &DuplicateDbg = *MBBIter; diff --git a/lib/CodeGen/BreakFalseDeps.cpp b/lib/CodeGen/BreakFalseDeps.cpp index 1e30a08b9dc..2e6d7275c7e 100644 --- a/lib/CodeGen/BreakFalseDeps.cpp +++ b/lib/CodeGen/BreakFalseDeps.cpp @@ -176,7 +176,7 @@ bool BreakFalseDeps::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx, } void BreakFalseDeps::processDefs(MachineInstr *MI) { - assert(!MI->isDebugValue() && "Won't process debug values"); + assert(!MI->isDebugInstr() && "Won't process debug values"); // Break dependence on undef uses. Do this before updating LiveRegs below. unsigned OpNum; @@ -244,7 +244,7 @@ void BreakFalseDeps::processBasicBlock(MachineBasicBlock *MBB) { // and by then we'll have better information, so we can avoid doing the work // to try and break dependencies now. for (MachineInstr &MI : *MBB) { - if (!MI.isDebugValue()) + if (!MI.isDebugInstr()) processDefs(&MI); } processUndefReads(MBB); diff --git a/lib/CodeGen/CalcSpillWeights.cpp b/lib/CodeGen/CalcSpillWeights.cpp index b8920a60193..5a9026926d6 100644 --- a/lib/CodeGen/CalcSpillWeights.cpp +++ b/lib/CodeGen/CalcSpillWeights.cpp @@ -236,7 +236,7 @@ float VirtRegAuxInfo::weightCalcHelper(LiveInterval &li, SlotIndex *start, continue; numInstr++; - if (mi->isIdentityCopy() || mi->isImplicitDef() || mi->isDebugValue()) + if (mi->isIdentityCopy() || mi->isImplicitDef() || mi->isDebugInstr()) continue; if (!visited.insert(mi).second) continue; diff --git a/lib/CodeGen/CriticalAntiDepBreaker.cpp b/lib/CodeGen/CriticalAntiDepBreaker.cpp index 5a4e6d0aad9..608fc4ba89b 100644 --- a/lib/CodeGen/CriticalAntiDepBreaker.cpp +++ b/lib/CodeGen/CriticalAntiDepBreaker.cpp @@ -113,7 +113,7 @@ void CriticalAntiDepBreaker::Observe(MachineInstr &MI, unsigned Count, // FIXME: It may be possible to remove the isKill() restriction once PR18663 // has been properly fixed. There can be value in processing kills as seen in // the AggressiveAntiDepBreaker class. - if (MI.isDebugValue() || MI.isKill()) + if (MI.isDebugInstr() || MI.isKill()) return; assert(Count < InsertPosIndex && "Instruction index out of expected range!"); @@ -534,7 +534,7 @@ BreakAntiDependencies(const std::vector<SUnit> &SUnits, // FIXME: It may be possible to remove the isKill() restriction once PR18663 // has been properly fixed. There can be value in processing kills as seen // in the AggressiveAntiDepBreaker class. - if (MI.isDebugValue() || MI.isKill()) + if (MI.isDebugInstr() || MI.isKill()) continue; // Check if this instruction has a dependence on the critical path that diff --git a/lib/CodeGen/EarlyIfConversion.cpp b/lib/CodeGen/EarlyIfConversion.cpp index 6294ff45011..c0c67c40376 100644 --- a/lib/CodeGen/EarlyIfConversion.cpp +++ b/lib/CodeGen/EarlyIfConversion.cpp @@ -195,7 +195,7 @@ bool SSAIfConv::canSpeculateInstrs(MachineBasicBlock *MBB) { // terminators never have side effects or define any used register values. for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->getFirstTerminator(); I != E; ++I) { - if (I->isDebugValue()) + if (I->isDebugInstr()) continue; if (++InstrCount > BlockInstrLimit && !Stress) { diff --git a/lib/CodeGen/ExecutionDomainFix.cpp b/lib/CodeGen/ExecutionDomainFix.cpp index 776fc6bb410..6413489e9d9 100644 --- a/lib/CodeGen/ExecutionDomainFix.cpp +++ b/lib/CodeGen/ExecutionDomainFix.cpp @@ -233,7 +233,7 @@ bool ExecutionDomainFix::visitInstr(MachineInstr *MI) { } void ExecutionDomainFix::processDefs(MachineInstr *MI, bool Kill) { - assert(!MI->isDebugValue() && "Won't process debug values"); + assert(!MI->isDebugInstr() && "Won't process debug values"); const MCInstrDesc &MCID = MI->getDesc(); for (unsigned i = 0, e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs(); @@ -401,7 +401,7 @@ void ExecutionDomainFix::processBasicBlock( // and by then we'll have better information, so we can avoid doing the work // to try and break dependencies now. for (MachineInstr &MI : *TraversedMBB.MBB) { - if (!MI.isDebugValue()) { + if (!MI.isDebugInstr()) { bool Kill = false; if (TraversedMBB.PrimaryPass) Kill = visitInstr(&MI); diff --git a/lib/CodeGen/IfConversion.cpp b/lib/CodeGen/IfConversion.cpp index 5b830ff359f..0ae28abc7f1 100644 --- a/lib/CodeGen/IfConversion.cpp +++ b/lib/CodeGen/IfConversion.cpp @@ -948,7 +948,7 @@ void IfConverter::ScanInstructions(BBInfo &BBI, BBI.ExtraCost2 = 0; BBI.ClobbersPred = false; for (MachineInstr &MI : make_range(Begin, End)) { - if (MI.isDebugValue()) + if (MI.isDebugInstr()) continue; // It's unsafe to duplicate convergent instructions in this context, so set @@ -1726,14 +1726,14 @@ bool IfConverter::IfConvertDiamondCommon( for (unsigned i = 0; i < NumDups1; ++DI1) { if (DI1 == MBB1.end()) break; - if (!DI1->isDebugValue()) + if (!DI1->isDebugInstr()) ++i; } while (NumDups1 != 0) { ++DI2; if (DI2 == MBB2.end()) break; - if (!DI2->isDebugValue()) + if (!DI2->isDebugInstr()) --NumDups1; } @@ -1767,7 +1767,7 @@ bool IfConverter::IfConvertDiamondCommon( assert(DI1 != MBB1.begin()); --DI1; // skip dbg_value instructions - if (!DI1->isDebugValue()) + if (!DI1->isDebugInstr()) ++i; } MBB1.erase(DI1, MBB1.end()); @@ -1782,7 +1782,7 @@ bool IfConverter::IfConvertDiamondCommon( // instructions could be found. while (DI2 != MBB2.begin()) { MachineBasicBlock::iterator Prev = std::prev(DI2); - if (!Prev->isBranch() && !Prev->isDebugValue()) + if (!Prev->isBranch() && !Prev->isDebugInstr()) break; DI2 = Prev; } @@ -1793,7 +1793,7 @@ bool IfConverter::IfConvertDiamondCommon( assert(DI2 != MBB2.begin()); --DI2; // skip dbg_value instructions - if (!DI2->isDebugValue()) + if (!DI2->isDebugInstr()) --NumDups2; } @@ -1809,7 +1809,7 @@ bool IfConverter::IfConvertDiamondCommon( SmallSet<unsigned, 4> ExtUses; if (TII->isProfitableToUnpredicate(MBB1, MBB2)) { for (const MachineInstr &FI : make_range(MBB2.begin(), DI2)) { - if (FI.isDebugValue()) + if (FI.isDebugInstr()) continue; SmallVector<unsigned, 4> Defs; for (const MachineOperand &MO : FI.operands()) { @@ -2002,7 +2002,7 @@ void IfConverter::PredicateBlock(BBInfo &BBI, bool AnyUnpred = false; bool MaySpec = LaterRedefs != nullptr; for (MachineInstr &I : make_range(BBI.BB->begin(), E)) { - if (I.isDebugValue() || TII->isPredicated(I)) + if (I.isDebugInstr() || TII->isPredicated(I)) continue; // It may be possible not to predicate an instruction if it's the 'true' // side of a diamond and the 'false' side may re-define the instruction's @@ -2058,7 +2058,7 @@ void IfConverter::CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI, ToBBI.ExtraCost += NumCycles-1; ToBBI.ExtraCost2 += ExtraPredCost; - if (!TII->isPredicated(I) && !MI->isDebugValue()) { + if (!TII->isPredicated(I) && !MI->isDebugInstr()) { if (!TII->PredicateInstruction(*MI, Cond)) { #ifndef NDEBUG dbgs() << "Unable to predicate " << I << "!\n"; diff --git a/lib/CodeGen/InlineSpiller.cpp b/lib/CodeGen/InlineSpiller.cpp index dc2d56818a8..3939e235995 100644 --- a/lib/CodeGen/InlineSpiller.cpp +++ b/lib/CodeGen/InlineSpiller.cpp @@ -617,7 +617,7 @@ void InlineSpiller::reMaterializeAll() { MachineInstr &MI = *RegI++; // Debug values are not allowed to affect codegen. - if (MI.isDebugValue()) + if (MI.isDebugInstr()) continue; anyRemat |= reMaterializeFor(LI, MI); @@ -932,7 +932,7 @@ void InlineSpiller::spillAroundUses(unsigned Reg) { MachineInstr *MI = &*(RegI++); // Debug values are not allowed to affect codegen. - if (MI->isDebugValue()) { + if (MI->isDebugInstr()) { // Modify DBG_VALUE now that the value is in a spill slot. MachineBasicBlock *MBB = MI->getParent(); DEBUG(dbgs() << "Modifying debug info due to spill:\t" << *MI); diff --git a/lib/CodeGen/LiveIntervals.cpp b/lib/CodeGen/LiveIntervals.cpp index 6f992666c56..ed0a62b99f2 100644 --- a/lib/CodeGen/LiveIntervals.cpp +++ b/lib/CodeGen/LiveIntervals.cpp @@ -1391,7 +1391,7 @@ private: MachineBasicBlock::iterator Begin = MBB->begin(); while (MII != Begin) { - if ((--MII)->isDebugValue()) + if ((--MII)->isDebugInstr()) continue; SlotIndex Idx = Indexes->getInstructionIndex(*MII); @@ -1453,7 +1453,7 @@ void LiveIntervals::repairOldRegInRange(const MachineBasicBlock::iterator Begin, for (MachineBasicBlock::iterator I = End; I != Begin;) { --I; MachineInstr &MI = *I; - if (MI.isDebugValue()) + if (MI.isDebugInstr()) continue; SlotIndex instrIdx = getInstructionIndex(MI); @@ -1550,7 +1550,7 @@ LiveIntervals::repairIntervalsInRange(MachineBasicBlock *MBB, for (MachineBasicBlock::iterator I = End; I != Begin;) { --I; MachineInstr &MI = *I; - if (MI.isDebugValue()) + if (MI.isDebugInstr()) continue; for (MachineInstr::const_mop_iterator MOI = MI.operands_begin(), MOE = MI.operands_end(); diff --git a/lib/CodeGen/LiveRangeShrink.cpp b/lib/CodeGen/LiveRangeShrink.cpp index 02e1f3b01ad..1aa3bbd90a9 100644 --- a/lib/CodeGen/LiveRangeShrink.cpp +++ b/lib/CodeGen/LiveRangeShrink.cpp @@ -130,7 +130,7 @@ bool LiveRangeShrink::runOnMachineFunction(MachineFunction &MF) { for (MachineBasicBlock::iterator Next = MBB.begin(); Next != MBB.end();) { MachineInstr &MI = *Next; ++Next; - if (MI.isPHI() || MI.isDebugValue()) + if (MI.isPHI() || MI.isDebugInstr()) continue; if (MI.mayStore()) SawStore = true; @@ -218,7 +218,7 @@ bool LiveRangeShrink::runOnMachineFunction(MachineFunction &MF) { if (DefMO && Insert && NumEligibleUse > 1 && Barrier <= IOM[Insert]) { MachineBasicBlock::iterator I = std::next(Insert->getIterator()); // Skip all the PHI and debug instructions. - while (I != MBB.end() && (I->isPHI() || I->isDebugValue())) + while (I != MBB.end() && (I->isPHI() || I->isDebugInstr())) I = std::next(I); if (I == MI.getIterator()) continue; diff --git a/lib/CodeGen/LiveVariables.cpp b/lib/CodeGen/LiveVariables.cpp index 87bb08a2fd4..0b92eab8380 100644 --- a/lib/CodeGen/LiveVariables.cpp +++ b/lib/CodeGen/LiveVariables.cpp @@ -499,7 +499,7 @@ void LiveVariables::UpdatePhysRegDefs(MachineInstr &MI, void LiveVariables::runOnInstr(MachineInstr &MI, SmallVectorImpl<unsigned> &Defs) { - assert(!MI.isDebugValue()); + assert(!MI.isDebugInstr()); // Process all of the operands of the instruction... unsigned NumOperandsToProcess = MI.getNumOperands(); @@ -576,7 +576,7 @@ void LiveVariables::runOnBlock(MachineBasicBlock *MBB, const unsigned NumRegs) { DistanceMap.clear(); unsigned Dist = 0; for (MachineInstr &MI : *MBB) { - if (MI.isDebugValue()) + if (MI.isDebugInstr()) continue; DistanceMap.insert(std::make_pair(&MI, Dist++)); diff --git a/lib/CodeGen/LocalStackSlotAllocation.cpp b/lib/CodeGen/LocalStackSlotAllocation.cpp index e95fc7f8cdf..b2a0d21e023 100644 --- a/lib/CodeGen/LocalStackSlotAllocation.cpp +++ b/lib/CodeGen/LocalStackSlotAllocation.cpp @@ -304,7 +304,7 @@ bool LocalStackSlotPass::insertFrameReferenceRegisters(MachineFunction &Fn) { for (MachineInstr &MI : BB) { // Debug value, stackmap and patchpoint instructions can't be out of // range, so they don't need any updates. - if (MI.isDebugValue() || MI.getOpcode() == TargetOpcode::STATEPOINT || + if (MI.isDebugInstr() || MI.getOpcode() == TargetOpcode::STATEPOINT || MI.getOpcode() == TargetOpcode::STACKMAP || MI.getOpcode() == TargetOpcode::PATCHPOINT) continue; diff --git a/lib/CodeGen/MachineBasicBlock.cpp b/lib/CodeGen/MachineBasicBlock.cpp index 6fa48c51866..319174de2d8 100644 --- a/lib/CodeGen/MachineBasicBlock.cpp +++ b/lib/CodeGen/MachineBasicBlock.cpp @@ -174,7 +174,7 @@ MachineBasicBlock::SkipPHIsLabelsAndDebug(MachineBasicBlock::iterator I) { const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo(); iterator E = end(); - while (I != E && (I->isPHI() || I->isPosition() || I->isDebugValue() || + while (I != E && (I->isPHI() || I->isPosition() || I->isDebugInstr() || TII->isBasicBlockPrologue(*I))) ++I; // FIXME: This needs to change if we wish to bundle labels / dbg_values @@ -187,7 +187,7 @@ MachineBasicBlock::SkipPHIsLabelsAndDebug(MachineBasicBlock::iterator I) { MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator() { iterator B = begin(), E = end(), I = E; - while (I != B && ((--I)->isTerminator() || I->isDebugValue())) + while (I != B && ((--I)->isTerminator() || I->isDebugInstr())) ; /*noop */ while (I != E && !I->isTerminator()) ++I; @@ -196,7 +196,7 @@ MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator() { MachineBasicBlock::instr_iterator MachineBasicBlock::getFirstInstrTerminator() { instr_iterator B = instr_begin(), E = instr_end(), I = E; - while (I != B && ((--I)->isTerminator() || I->isDebugValue())) + while (I != B && ((--I)->isTerminator() || I->isDebugInstr())) ; /*noop */ while (I != E && !I->isTerminator()) ++I; @@ -214,7 +214,7 @@ MachineBasicBlock::iterator MachineBasicBlock::getLastNonDebugInstr() { while (I != B) { --I; // Return instruction that starts a bundle. - if (I->isDebugValue() || I->isInsideBundle()) + if (I->isDebugInstr() || I->isInsideBundle()) continue; return I; } @@ -1271,7 +1271,7 @@ DebugLoc MachineBasicBlock::findPrevDebugLoc(instr_iterator MBBI) { if (MBBI == instr_begin()) return {}; // Skip debug declarations, we don't want a DebugLoc from them. MBBI = skipDebugInstructionsBackward(std::prev(MBBI), instr_begin()); - if (!MBBI->isDebugValue()) return MBBI->getDebugLoc(); + if (!MBBI->isDebugInstr()) return MBBI->getDebugLoc(); return {}; } diff --git a/lib/CodeGen/MachineCSE.cpp b/lib/CodeGen/MachineCSE.cpp index ce8503427ea..75a3d071bdc 100644 --- a/lib/CodeGen/MachineCSE.cpp +++ b/lib/CodeGen/MachineCSE.cpp @@ -314,7 +314,7 @@ bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI, unsigned LookAheadLeft = LookAheadLimit; while (LookAheadLeft) { // Skip over dbg_value's. - while (I != E && I != EE && I->isDebugValue()) + while (I != E && I != EE && I->isDebugInstr()) ++I; if (I == EE) { @@ -353,7 +353,7 @@ bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI, bool MachineCSE::isCSECandidate(MachineInstr *MI) { if (MI->isPosition() || MI->isPHI() || MI->isImplicitDef() || MI->isKill() || - MI->isInlineAsm() || MI->isDebugValue()) + MI->isInlineAsm() || MI->isDebugInstr()) return false; // Ignore copies. diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp index c0e1a7bef04..9686018b1fe 100644 --- a/lib/CodeGen/MachineInstr.cpp +++ b/lib/CodeGen/MachineInstr.cpp @@ -467,8 +467,8 @@ bool MachineInstr::isIdenticalTo(const MachineInstr &Other, return false; } } - // If DebugLoc does not match then two dbg.values are not identical. - if (isDebugValue()) + // If DebugLoc does not match then two debug instructions are not identical. + if (isDebugInstr()) if (getDebugLoc() && Other.getDebugLoc() && getDebugLoc() != Other.getDebugLoc()) return false; @@ -975,7 +975,7 @@ bool MachineInstr::isSafeToMove(AliasAnalysis *AA, bool &SawStore) const { return false; } - if (isPosition() || isDebugValue() || isTerminator() || + if (isPosition() || isDebugInstr() || isTerminator() || hasUnmodeledSideEffects()) return false; @@ -1534,6 +1534,7 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST, if (isIndirectDebugValue()) OS << " indirect"; } + // TODO: DBG_LABEL if (AddNewLine) OS << '\n'; diff --git a/lib/CodeGen/MachineScheduler.cpp b/lib/CodeGen/MachineScheduler.cpp index f80d6a695a5..cee87be9249 100644 --- a/lib/CodeGen/MachineScheduler.cpp +++ b/lib/CodeGen/MachineScheduler.cpp @@ -272,7 +272,7 @@ priorNonDebug(MachineBasicBlock::const_iterator I, MachineBasicBlock::const_iterator Beg) { assert(I != Beg && "reached the top of the region, cannot decrement"); while (--I != Beg) { - if (!I->isDebugValue()) + if (!I->isDebugInstr()) break; } return I; @@ -292,7 +292,7 @@ static MachineBasicBlock::const_iterator nextIfDebug(MachineBasicBlock::const_iterator I, MachineBasicBlock::const_iterator End) { for(; I != End; ++I) { - if (!I->isDebugValue()) + if (!I->isDebugInstr()) break; } return I; @@ -482,7 +482,7 @@ getSchedRegions(MachineBasicBlock *MBB, MachineInstr &MI = *std::prev(I); if (isSchedBoundary(&MI, &*MBB, MF, TII)) break; - if (!MI.isDebugValue()) + if (!MI.isDebugInstr()) // MBB::size() uses instr_iterator to count. Here we need a bundle to // count as a single instruction. ++NumRegionInstrs; @@ -1055,7 +1055,7 @@ void ScheduleDAGMILive::initRegPressure() { ); assert((BotRPTracker.getPos() == RegionEnd || - (RegionEnd->isDebugValue() && + (RegionEnd->isDebugInstr() && BotRPTracker.getPos() == priorNonDebug(RegionEnd, RegionBegin))) && "Can't find the region bottom"); diff --git a/lib/CodeGen/MachineSink.cpp b/lib/CodeGen/MachineSink.cpp index 0e5c839c180..0d43b10cc84 100644 --- a/lib/CodeGen/MachineSink.cpp +++ b/lib/CodeGen/MachineSink.cpp @@ -372,7 +372,7 @@ bool MachineSinking::ProcessBlock(MachineBasicBlock &MBB) { if (!ProcessedBegin) --I; - if (MI.isDebugValue()) + if (MI.isDebugInstr()) continue; bool Joined = PerformTrivialForwardCoalescing(MI, &MBB); diff --git a/lib/CodeGen/MachineTraceMetrics.cpp b/lib/CodeGen/MachineTraceMetrics.cpp index 1de06727325..f4aebca3f47 100644 --- a/lib/CodeGen/MachineTraceMetrics.cpp +++ b/lib/CodeGen/MachineTraceMetrics.cpp @@ -653,7 +653,7 @@ static bool getDataDeps(const MachineInstr &UseMI, SmallVectorImpl<DataDep> &Deps, const MachineRegisterInfo *MRI) { // Debug values should not be included in any calculations. - if (UseMI.isDebugValue()) + if (UseMI.isDebugInstr()) return false; bool HasPhysRegs = false; diff --git a/lib/CodeGen/MachineVerifier.cpp b/lib/CodeGen/MachineVerifier.cpp index 8d518571d24..03b5e8c7779 100644 --- a/lib/CodeGen/MachineVerifier.cpp +++ b/lib/CodeGen/MachineVerifier.cpp @@ -902,7 +902,7 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) { // Other instructions must have one, unless they are inside a bundle. if (LiveInts) { bool mapped = !LiveInts->isNotInMIMap(*MI); - if (MI->isDebugValue()) { + if (MI->isDebugInstr()) { if (mapped) report("Debug instruction has a slot index", MI); } else if (MI->isInsideBundle()) { diff --git a/lib/CodeGen/PHIElimination.cpp b/lib/CodeGen/PHIElimination.cpp index 54c5a940275..6a73708b9a8 100644 --- a/lib/CodeGen/PHIElimination.cpp +++ b/lib/CodeGen/PHIElimination.cpp @@ -452,7 +452,7 @@ void PHIElimination::LowerPHINode(MachineBasicBlock &MBB, KillInst = FirstTerm; while (KillInst != opBlock.begin()) { --KillInst; - if (KillInst->isDebugValue()) + if (KillInst->isDebugInstr()) continue; if (KillInst->readsRegister(SrcReg)) break; @@ -512,7 +512,7 @@ void PHIElimination::LowerPHINode(MachineBasicBlock &MBB, KillInst = FirstTerm; while (KillInst != opBlock.begin()) { --KillInst; - if (KillInst->isDebugValue()) + if (KillInst->isDebugInstr()) continue; if (KillInst->readsRegister(SrcReg)) break; diff --git a/lib/CodeGen/PeepholeOptimizer.cpp b/lib/CodeGen/PeepholeOptimizer.cpp index 5ce7da8f6c5..d7d792e58bf 100644 --- a/lib/CodeGen/PeepholeOptimizer.cpp +++ b/lib/CodeGen/PeepholeOptimizer.cpp @@ -1643,8 +1643,8 @@ bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) { ++MII; LocalMIs.insert(MI); - // Skip debug values. They should not affect this peephole optimization. - if (MI->isDebugValue()) + // Skip debug instructions. They should not affect this peephole optimization. + if (MI->isDebugInstr()) continue; if (MI->isPosition()) diff --git a/lib/CodeGen/ReachingDefAnalysis.cpp b/lib/CodeGen/ReachingDefAnalysis.cpp index a2275625a04..31eb8c9b264 100644 --- a/lib/CodeGen/ReachingDefAnalysis.cpp +++ b/lib/CodeGen/ReachingDefAnalysis.cpp @@ -93,7 +93,7 @@ void ReachingDefAnalysis::leaveBasicBlock( } void ReachingDefAnalysis::processDefs(MachineInstr *MI) { - assert(!MI->isDebugValue() && "Won't process debug values"); + assert(!MI->isDebugInstr() && "Won't process debug instructions"); unsigned MBBNumber = MI->getParent()->getNumber(); assert(MBBNumber < MBBReachingDefs.size() && @@ -125,7 +125,7 @@ void ReachingDefAnalysis::processBasicBlock( const LoopTraversal::TraversedMBBInfo &TraversedMBB) { enterBasicBlock(TraversedMBB); for (MachineInstr &MI : *TraversedMBB.MBB) { - if (!MI.isDebugValue()) + if (!MI.isDebugInstr()) processDefs(&MI); } leaveBasicBlock(TraversedMBB); diff --git a/lib/CodeGen/RegAllocFast.cpp b/lib/CodeGen/RegAllocFast.cpp index 78b94a25210..241f680e2e8 100644 --- a/lib/CodeGen/RegAllocFast.cpp +++ b/lib/CodeGen/RegAllocFast.cpp @@ -910,6 +910,9 @@ void RegAllocFast::allocateBasicBlock(MachineBasicBlock &MBB) { continue; } + if (MI.isDebugLabel()) + continue; + // If this is a copy, we may be able to coalesce. unsigned CopySrcReg = 0; unsigned CopyDstReg = 0; diff --git a/lib/CodeGen/RegisterCoalescer.cpp b/lib/CodeGen/RegisterCoalescer.cpp index c0deb11d06d..a9565fae8f1 100644 --- a/lib/CodeGen/RegisterCoalescer.cpp +++ b/lib/CodeGen/RegisterCoalescer.cpp @@ -2578,7 +2578,7 @@ taintExtent(unsigned ValNo, LaneBitmask TaintedLanes, JoinVals &Other, bool JoinVals::usesLanes(const MachineInstr &MI, unsigned Reg, unsigned SubIdx, LaneBitmask Lanes) const { - if (MI.isDebugValue()) + if (MI.isDebugInstr()) return false; for (const MachineOperand &MO : MI.operands()) { if (!MO.isReg() || MO.isDef() || MO.getReg() != Reg) diff --git a/lib/CodeGen/RegisterPressure.cpp b/lib/CodeGen/RegisterPressure.cpp index 3dbdd937b39..51414de518f 100644 --- a/lib/CodeGen/RegisterPressure.cpp +++ b/lib/CodeGen/RegisterPressure.cpp @@ -748,7 +748,7 @@ void RegPressureTracker::bumpDeadDefs(ArrayRef<RegisterMaskPair> DeadDefs) { /// instruction independent of liveness. void RegPressureTracker::recede(const RegisterOperands &RegOpers, SmallVectorImpl<RegisterMaskPair> *LiveUses) { - assert(!CurrPos->isDebugValue()); + assert(!CurrPos->isDebugInstr()); // Boost pressure for all dead defs together. bumpDeadDefs(RegOpers.DeadDefs); @@ -1019,7 +1019,7 @@ static void computeMaxPressureDelta(ArrayRef<unsigned> OldMaxPressureVec, /// This is intended for speculative queries. It leaves pressure inconsistent /// with the current position, so must be restored by the caller. void RegPressureTracker::bumpUpwardPressure(const MachineInstr *MI) { - assert(!MI->isDebugValue() && "Expect a nondebug instruction."); + assert(!MI->isDebugInstr() && "Expect a nondebug instruction."); SlotIndex SlotIdx; if (RequireIntervals) @@ -1260,7 +1260,7 @@ LaneBitmask RegPressureTracker::getLiveThroughAt(unsigned RegUnit, /// This is intended for speculative queries. It leaves pressure inconsistent /// with the current position, so must be restored by the caller. void RegPressureTracker::bumpDownwardPressure(const MachineInstr *MI) { - assert(!MI->isDebugValue() && "Expect a nondebug instruction."); + assert(!MI->isDebugInstr() && "Expect a nondebug instruction."); SlotIndex SlotIdx; if (RequireIntervals) diff --git a/lib/CodeGen/RegisterScavenging.cpp b/lib/CodeGen/RegisterScavenging.cpp index 97967124add..9fa14c9dc5e 100644 --- a/lib/CodeGen/RegisterScavenging.cpp +++ b/lib/CodeGen/RegisterScavenging.cpp @@ -111,7 +111,7 @@ void RegScavenger::determineKillsAndDefs() { assert(Tracking && "Must be tracking to determine kills and defs"); MachineInstr &MI = *MBBI; - assert(!MI.isDebugValue() && "Debug values have no kills or defs"); + assert(!MI.isDebugInstr() && "Debug values have no kills or defs"); // Find out which registers are early clobbered, killed, defined, and marked // def-dead in this instruction. @@ -158,7 +158,7 @@ void RegScavenger::unprocess() { assert(Tracking && "Cannot unprocess because we're not tracking"); MachineInstr &MI = *MBBI; - if (!MI.isDebugValue()) { + if (!MI.isDebugInstr()) { determineKillsAndDefs(); // Commit the changes. @@ -195,7 +195,7 @@ void RegScavenger::forward() { I->Restore = nullptr; } - if (MI.isDebugValue()) + if (MI.isDebugInstr()) return; determineKillsAndDefs(); @@ -318,7 +318,7 @@ unsigned RegScavenger::findSurvivorReg(MachineBasicBlock::iterator StartMI, bool inVirtLiveRange = false; for (++MI; InstrLimit > 0 && MI != ME; ++MI, --InstrLimit) { - if (MI->isDebugValue()) { + if (MI->isDebugInstr()) { ++InstrLimit; // Don't count debug instructions continue; } diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp index 45df5c9d0b5..d08501fa3c4 100644 --- a/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -533,7 +533,7 @@ void ScheduleDAGInstrs::initSUnits() { SUnits.reserve(NumRegionInstrs); for (MachineInstr &MI : make_range(RegionBegin, RegionEnd)) { - if (MI.isDebugValue()) + if (MI.isDebugInstr()) continue; SUnit *SU = newSUnit(&MI); @@ -764,6 +764,9 @@ void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA, DbgMI = &MI; continue; } + if (MI.isDebugLabel()) + continue; + SUnit *SU = MISUnitMap[&MI]; assert(SU && "No SUnit mapped to this MI"); @@ -1052,7 +1055,7 @@ void ScheduleDAGInstrs::fixupKills(MachineBasicBlock &MBB) { // Examine block from end to start... for (MachineInstr &MI : make_range(MBB.rbegin(), MBB.rend())) { - if (MI.isDebugValue()) + if (MI.isDebugInstr()) continue; // Update liveness. Registers that are defed but not used in this @@ -1088,7 +1091,7 @@ void ScheduleDAGInstrs::fixupKills(MachineBasicBlock &MBB) { while (I->isBundledWithSucc()) ++I; do { - if (!I->isDebugValue()) + if (!I->isDebugInstr()) toggleKills(MRI, LiveRegs, *I, true); --I; } while(I != First); diff --git a/lib/CodeGen/SlotIndexes.cpp b/lib/CodeGen/SlotIndexes.cpp index 5556a7ed904..ff706a6a655 100644 --- a/lib/CodeGen/SlotIndexes.cpp +++ b/lib/CodeGen/SlotIndexes.cpp @@ -74,7 +74,7 @@ bool SlotIndexes::runOnMachineFunction(MachineFunction &fn) { SlotIndex blockStartIndex(&indexList.back(), SlotIndex::Slot_Block); for (MachineInstr &MI : MBB) { - if (MI.isDebugValue()) + if (MI.isDebugInstr()) continue; // Insert a store index for the instr. @@ -245,7 +245,7 @@ void SlotIndexes::repairIndexesInRange(MachineBasicBlock *MBB, for (MachineBasicBlock::iterator I = End; I != Begin;) { --I; MachineInstr &MI = *I; - if (!MI.isDebugValue() && mi2iMap.find(&MI) == mi2iMap.end()) + if (!MI.isDebugInstr() && mi2iMap.find(&MI) == mi2iMap.end()) insertMachineInstrInMaps(MI); } } diff --git a/lib/CodeGen/SplitKit.cpp b/lib/CodeGen/SplitKit.cpp index 1f7e469dfca..9c0b6c39952 100644 --- a/lib/CodeGen/SplitKit.cpp +++ b/lib/CodeGen/SplitKit.cpp @@ -860,7 +860,7 @@ void SplitEditor::removeBackCopies(SmallVectorImpl<VNInfo*> &Copies) { MachineBasicBlock::iterator MBBI(MI); bool AtBegin; do AtBegin = MBBI == MBB->begin(); - while (!AtBegin && (--MBBI)->isDebugValue()); + while (!AtBegin && (--MBBI)->isDebugInstr()); DEBUG(dbgs() << "Removing " << Def << '\t' << *MI); LIS.removeVRegDefAt(*LI, Def); diff --git a/lib/CodeGen/StackColoring.cpp b/lib/CodeGen/StackColoring.cpp index d9d071b59f9..e9eb6005827 100644 --- a/lib/CodeGen/StackColoring.cpp +++ b/lib/CodeGen/StackColoring.cpp @@ -606,7 +606,7 @@ bool StackColoring::isLifetimeStartOrEnd(const MachineInstr &MI, return true; } } else if (LifetimeStartOnFirstUse && !ProtectFromEscapedAllocas) { - if (!MI.isDebugValue()) { + if (!MI.isDebugInstr()) { bool found = false; for (const MachineOperand &MO : MI.operands()) { if (!MO.isFI()) @@ -1000,7 +1000,7 @@ void StackColoring::remapInstructions(DenseMap<int, int> &SlotRemap) { bool TouchesMemory = I.mayLoad() || I.mayStore(); // If we *don't* protect the user from escaped allocas, don't bother // validating the instructions. - if (!I.isDebugValue() && TouchesMemory && ProtectFromEscapedAllocas) { + if (!I.isDebugInstr() && TouchesMemory && ProtectFromEscapedAllocas) { SlotIndex Index = Indexes->getInstructionIndex(I); const LiveInterval *Interval = &*Intervals[FromSlot]; assert(Interval->find(Index) != Interval->end() && @@ -1074,7 +1074,7 @@ void StackColoring::removeInvalidSlotRanges() { for (MachineBasicBlock &BB : *MF) for (MachineInstr &I : BB) { if (I.getOpcode() == TargetOpcode::LIFETIME_START || - I.getOpcode() == TargetOpcode::LIFETIME_END || I.isDebugValue()) + I.getOpcode() == TargetOpcode::LIFETIME_END || I.isDebugInstr()) continue; // Some intervals are suspicious! In some cases we find address diff --git a/lib/CodeGen/StackSlotColoring.cpp b/lib/CodeGen/StackSlotColoring.cpp index 17f6b83a619..cd13b3f7969 100644 --- a/lib/CodeGen/StackSlotColoring.cpp +++ b/lib/CodeGen/StackSlotColoring.cpp @@ -423,7 +423,7 @@ bool StackSlotColoring::RemoveDeadStores(MachineBasicBlock* MBB) { if (!(LoadReg = TII->isLoadFromStackSlot(*I, FirstSS, LoadSize))) continue; // Skip the ...pseudo debugging... instructions between a load and store. - while ((NextMI != E) && NextMI->isDebugValue()) { + while ((NextMI != E) && NextMI->isDebugInstr()) { ++NextMI; ++I; } diff --git a/lib/CodeGen/TwoAddressInstructionPass.cpp b/lib/CodeGen/TwoAddressInstructionPass.cpp index 539f8486192..da55c18854a 100644 --- a/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -290,8 +290,8 @@ sink3AddrInstruction(MachineInstr *MI, unsigned SavedReg, unsigned NumVisited = 0; for (MachineInstr &OtherMI : make_range(std::next(OldPos), KillPos)) { - // DBG_VALUE cannot be counted against the limit. - if (OtherMI.isDebugValue()) + // Debug instructions cannot be counted against the limit. + if (OtherMI.isDebugInstr()) continue; if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost. return false; @@ -940,8 +940,8 @@ rescheduleMIBelowKill(MachineBasicBlock::iterator &mi, MachineBasicBlock::iterator KillPos = KillMI; ++KillPos; for (MachineInstr &OtherMI : make_range(End, KillPos)) { - // DBG_VALUE cannot be counted against the limit. - if (OtherMI.isDebugValue()) + // Debug instructions cannot be counted against the limit. + if (OtherMI.isDebugInstr()) continue; if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost. return false; @@ -985,7 +985,7 @@ rescheduleMIBelowKill(MachineBasicBlock::iterator &mi, } // Move debug info as well. - while (Begin != MBB->begin() && std::prev(Begin)->isDebugValue()) + while (Begin != MBB->begin() && std::prev(Begin)->isDebugInstr()) --Begin; nmi = End; @@ -1114,8 +1114,8 @@ rescheduleKillAboveMI(MachineBasicBlock::iterator &mi, unsigned NumVisited = 0; for (MachineInstr &OtherMI : make_range(mi, MachineBasicBlock::iterator(KillMI))) { - // DBG_VALUE cannot be counted against the limit. - if (OtherMI.isDebugValue()) + // Debug instructions cannot be counted against the limit. + if (OtherMI.isDebugInstr()) continue; if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost. return false; @@ -1162,11 +1162,11 @@ rescheduleKillAboveMI(MachineBasicBlock::iterator &mi, // Move the old kill above MI, don't forget to move debug info as well. MachineBasicBlock::iterator InsertPos = mi; - while (InsertPos != MBB->begin() && std::prev(InsertPos)->isDebugValue()) + while (InsertPos != MBB->begin() && std::prev(InsertPos)->isDebugInstr()) --InsertPos; MachineBasicBlock::iterator From = KillMI; MachineBasicBlock::iterator To = std::next(From); - while (std::prev(From)->isDebugValue()) + while (std::prev(From)->isDebugInstr()) --From; MBB->splice(InsertPos, MBB, From, To); @@ -1699,7 +1699,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) { MachineBasicBlock::iterator nmi = std::next(mi); // Don't revisit an instruction previously converted by target. It may // contain undef register operands (%noreg), which are not handled. - if (mi->isDebugValue() || SunkInstrs.count(&*mi)) { + if (mi->isDebugInstr() || SunkInstrs.count(&*mi)) { mi = nmi; continue; } diff --git a/lib/Target/AArch64/AArch64ConditionalCompares.cpp b/lib/Target/AArch64/AArch64ConditionalCompares.cpp index b0bda7c43c1..9ff2472dbec 100644 --- a/lib/Target/AArch64/AArch64ConditionalCompares.cpp +++ b/lib/Target/AArch64/AArch64ConditionalCompares.cpp @@ -392,7 +392,7 @@ bool SSACCmpConv::canSpeculateInstrs(MachineBasicBlock *MBB, // Check all instructions, except the terminators. It is assumed that // terminators never have side effects or define any used register values. for (auto &I : make_range(MBB->begin(), MBB->getFirstTerminator())) { - if (I.isDebugValue()) + if (I.isDebugInstr()) continue; if (++InstrCount > BlockInstrLimit && !Stress) { diff --git a/lib/Target/AArch64/AArch64FrameLowering.cpp b/lib/Target/AArch64/AArch64FrameLowering.cpp index d233827078a..2523cfdfb53 100644 --- a/lib/Target/AArch64/AArch64FrameLowering.cpp +++ b/lib/Target/AArch64/AArch64FrameLowering.cpp @@ -162,7 +162,7 @@ static unsigned estimateRSStackSizeLimit(MachineFunction &MF) { // realistically that's not a big deal at this stage of the game. for (MachineBasicBlock &MBB : MF) { for (MachineInstr &MI : MBB) { - if (MI.isDebugValue() || MI.isPseudo() || + if (MI.isDebugInstr() || MI.isPseudo() || MI.getOpcode() == AArch64::ADDXri || MI.getOpcode() == AArch64::ADDSXri) continue; diff --git a/lib/Target/AArch64/AArch64InstrInfo.cpp b/lib/Target/AArch64/AArch64InstrInfo.cpp index 452bb13bf88..879d91d0d15 100644 --- a/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -5044,7 +5044,7 @@ AArch64InstrInfo::getOutliningType(MachineBasicBlock::iterator &MIT, return MachineOutlinerInstrType::Illegal; // Don't allow debug values to impact outlining type. - if (MI.isDebugValue() || MI.isIndirectDebugValue()) + if (MI.isDebugInstr() || MI.isIndirectDebugValue()) return MachineOutlinerInstrType::Invisible; // At this point, KILL instructions don't really tell us much so we can go diff --git a/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp index 9cb9045ca76..2a05e3baa62 100644 --- a/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp +++ b/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp @@ -511,7 +511,7 @@ uint64_t AMDGPUAsmPrinter::getFunctionCodeSize(const MachineFunction &MF) const // TODO: CodeSize should account for multiple functions. // TODO: Should we count size of debug info? - if (MI.isDebugValue()) + if (MI.isDebugInstr()) continue; CodeSize += TII->getInstSizeInBytes(MI); @@ -652,7 +652,7 @@ AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage( continue; case AMDGPU::NoRegister: - assert(MI.isDebugValue()); + assert(MI.isDebugInstr()); continue; case AMDGPU::VCC: diff --git a/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/lib/Target/AMDGPU/GCNHazardRecognizer.cpp index dd515b0bf2f..20f1321e79f 100644 --- a/lib/Target/AMDGPU/GCNHazardRecognizer.cpp +++ b/lib/Target/AMDGPU/GCNHazardRecognizer.cpp @@ -634,7 +634,7 @@ int GCNHazardRecognizer::checkRFEHazards(MachineInstr *RFE) { } int GCNHazardRecognizer::checkAnyInstHazards(MachineInstr *MI) { - if (MI->isDebugValue()) + if (MI->isDebugInstr()) return 0; const SIRegisterInfo *TRI = ST.getRegisterInfo(); diff --git a/lib/Target/AMDGPU/GCNIterativeScheduler.cpp b/lib/Target/AMDGPU/GCNIterativeScheduler.cpp index 9fecd8576f9..bf8413921d4 100644 --- a/lib/Target/AMDGPU/GCNIterativeScheduler.cpp +++ b/lib/Target/AMDGPU/GCNIterativeScheduler.cpp @@ -69,14 +69,14 @@ static void printRegion(raw_ostream &OS, auto I = Begin; MaxInstNum = std::max(MaxInstNum, 1u); for (; I != End && MaxInstNum; ++I, --MaxInstNum) { - if (!I->isDebugValue() && LIS) + if (!I->isDebugInstr() && LIS) OS << LIS->getInstructionIndex(*I); OS << '\t' << *I; } if (I != End) { OS << "\t...\n"; I = std::prev(End); - if (!I->isDebugValue() && LIS) + if (!I->isDebugInstr() && LIS) OS << LIS->getInstructionIndex(*I); OS << '\t' << *I; } @@ -384,10 +384,10 @@ void GCNIterativeScheduler::scheduleRegion(Region &R, Range &&Schedule, if (MI != &*Top) { BB->remove(MI); BB->insert(Top, MI); - if (!MI->isDebugValue()) + if (!MI->isDebugInstr()) LIS->handleMove(*MI, true); } - if (!MI->isDebugValue()) { + if (!MI->isDebugInstr()) { // Reset read - undef flags and update them later. for (auto &Op : MI->operands()) if (Op.isReg() && Op.isDef()) diff --git a/lib/Target/AMDGPU/GCNRegPressure.cpp b/lib/Target/AMDGPU/GCNRegPressure.cpp index a294ae075a2..4e569a27e97 100644 --- a/lib/Target/AMDGPU/GCNRegPressure.cpp +++ b/lib/Target/AMDGPU/GCNRegPressure.cpp @@ -301,7 +301,7 @@ void GCNUpwardRPTracker::recede(const MachineInstr &MI) { LastTrackedMI = &MI; - if (MI.isDebugValue()) + if (MI.isDebugInstr()) return; auto const RegUses = collectVirtualRegUses(MI, LIS, *MRI); diff --git a/lib/Target/AMDGPU/GCNSchedStrategy.cpp b/lib/Target/AMDGPU/GCNSchedStrategy.cpp index cd7ccb4ac31..f92788ebaa7 100644 --- a/lib/Target/AMDGPU/GCNSchedStrategy.cpp +++ b/lib/Target/AMDGPU/GCNSchedStrategy.cpp @@ -388,13 +388,13 @@ void GCNScheduleDAGMILive::schedule() { DEBUG(dbgs() << "Attempting to revert scheduling.\n"); RegionEnd = RegionBegin; for (MachineInstr *MI : Unsched) { - if (MI->isDebugValue()) + if (MI->isDebugInstr()) continue; if (MI->getIterator() != RegionEnd) { BB->remove(MI); BB->insert(RegionEnd, MI); - if (!MI->isDebugValue()) + if (!MI->isDebugInstr()) LIS->handleMove(*MI, true); } // Reset read-undef flags and update them later. @@ -403,7 +403,7 @@ void GCNScheduleDAGMILive::schedule() { Op.setIsUndef(false); RegisterOperands RegOpers; RegOpers.collect(*MI, *TRI, MRI, ShouldTrackLaneMasks, false); - if (!MI->isDebugValue()) { + if (!MI->isDebugInstr()) { if (ShouldTrackLaneMasks) { // Adjust liveness and add missing dead+read-undef flags. SlotIndex SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot(); diff --git a/lib/Target/AMDGPU/SIDebuggerInsertNops.cpp b/lib/Target/AMDGPU/SIDebuggerInsertNops.cpp index 69ec3816772..c8ae8f71adc 100644 --- a/lib/Target/AMDGPU/SIDebuggerInsertNops.cpp +++ b/lib/Target/AMDGPU/SIDebuggerInsertNops.cpp @@ -78,8 +78,8 @@ bool SIDebuggerInsertNops::runOnMachineFunction(MachineFunction &MF) { for (auto &MBB : MF) { for (auto MI = MBB.begin(); MI != MBB.end(); ++MI) { - // Skip DBG_VALUE instructions and instructions without location. - if (MI->isDebugValue() || !MI->getDebugLoc()) + // Skip debug instructions and instructions without location. + if (MI->isDebugInstr() || !MI->getDebugLoc()) continue; // Insert nop instruction if line number does not have nop inserted. diff --git a/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/lib/Target/AMDGPU/SIInsertWaitcnts.cpp index 7dc3b68e01d..e6aaaf94751 100644 --- a/lib/Target/AMDGPU/SIInsertWaitcnts.cpp +++ b/lib/Target/AMDGPU/SIInsertWaitcnts.cpp @@ -897,7 +897,7 @@ void SIInsertWaitcnts::generateWaitcntInstBefore( setForceEmitWaitcnt(); bool IsForceEmitWaitcnt = isForceEmitWaitcnt(); - if (MI.isDebugValue() && + if (MI.isDebugInstr() && // TODO: any other opcode? !NeedLineMapping) { return; diff --git a/lib/Target/AMDGPU/SIMachineScheduler.cpp b/lib/Target/AMDGPU/SIMachineScheduler.cpp index 04536cdfe72..0fd4c6bfed9 100644 --- a/lib/Target/AMDGPU/SIMachineScheduler.cpp +++ b/lib/Target/AMDGPU/SIMachineScheduler.cpp @@ -1280,7 +1280,7 @@ static MachineBasicBlock::iterator nextIfDebug(MachineBasicBlock::iterator I, MachineBasicBlock::const_iterator End) { for (; I != End; ++I) { - if (!I->isDebugValue()) + if (!I->isDebugInstr()) break; } return I; diff --git a/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp b/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp index 51ac8146f3a..b7bb80acb71 100644 --- a/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp +++ b/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp @@ -134,7 +134,7 @@ bool SIOptimizeExecMaskingPreRA::runOnMachineFunction(MachineFunction &MF) { } while (I != E) { - if (I->isDebugValue()) { + if (I->isDebugInstr()) { I = std::next(I); continue; } diff --git a/lib/Target/ARC/ARCInstrInfo.cpp b/lib/Target/ARC/ARCInstrInfo.cpp index 4a95fced446..f8d14d243f4 100644 --- a/lib/Target/ARC/ARCInstrInfo.cpp +++ b/lib/Target/ARC/ARCInstrInfo.cpp @@ -173,7 +173,7 @@ bool ARCInstrInfo::analyzeBranch(MachineBasicBlock &MBB, bool CantAnalyze = false; // Skip over DEBUG values and predicated nonterminators. - while (I->isDebugValue() || !I->isTerminator()) { + while (I->isDebugInstr() || !I->isTerminator()) { if (I == MBB.begin()) return false; --I; diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index 89e22369810..efe96f8d1b0 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -331,7 +331,7 @@ bool ARMBaseInstrInfo::analyzeBranch(MachineBasicBlock &MBB, bool CantAnalyze = false; // Skip over DEBUG values and predicated nonterminators. - while (I->isDebugValue() || !I->isTerminator()) { + while (I->isDebugInstr() || !I->isTerminator()) { if (I == MBB.begin()) return false; --I; @@ -1815,7 +1815,7 @@ bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr &MI, // considered a scheduling hazard, which is wrong. It should be the actual // instruction preceding the dbg_value instruction(s), just like it is // when debug info is not present. - if (MI.isDebugValue()) + if (MI.isDebugInstr()) return false; // Terminators and labels can't be scheduled around. @@ -1829,8 +1829,8 @@ bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr &MI, // to the t2IT instruction. The added compile time and complexity does not // seem worth it. MachineBasicBlock::const_iterator I = MI; - // Make sure to skip any dbg_value instructions - while (++I != MBB->end() && I->isDebugValue()) + // Make sure to skip any debug instructions + while (++I != MBB->end() && I->isDebugInstr()) ; if (I != MBB->end() && I->getOpcode() == ARM::t2IT) return true; diff --git a/lib/Target/ARM/ARMConstantIslandPass.cpp b/lib/Target/ARM/ARMConstantIslandPass.cpp index 7411caf4d12..1e3655aac89 100644 --- a/lib/Target/ARM/ARMConstantIslandPass.cpp +++ b/lib/Target/ARM/ARMConstantIslandPass.cpp @@ -701,7 +701,7 @@ initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs) { WaterList.push_back(&MBB); for (MachineInstr &I : MBB) { - if (I.isDebugValue()) + if (I.isDebugInstr()) continue; unsigned Opc = I.getOpcode(); diff --git a/lib/Target/ARM/ARMHazardRecognizer.cpp b/lib/Target/ARM/ARMHazardRecognizer.cpp index f878bf9937a..d5dacbe0877 100644 --- a/lib/Target/ARM/ARMHazardRecognizer.cpp +++ b/lib/Target/ARM/ARMHazardRecognizer.cpp @@ -37,7 +37,7 @@ ARMHazardRecognizer::getHazardType(SUnit *SU, int Stalls) { MachineInstr *MI = SU->getInstr(); - if (!MI->isDebugValue()) { + if (!MI->isDebugInstr()) { // Look for special VMLA / VMLS hazards. A VMUL / VADD / VSUB following // a VMLA / VMLS will cause 4 cycle stall. const MCInstrDesc &MCID = MI->getDesc(); @@ -81,7 +81,7 @@ void ARMHazardRecognizer::Reset() { void ARMHazardRecognizer::EmitInstruction(SUnit *SU) { MachineInstr *MI = SU->getInstr(); - if (!MI->isDebugValue()) { + if (!MI->isDebugInstr()) { LastMI = MI; FpMLxStalls = 0; } diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index bd478702c61..174ed3e5dd2 100644 --- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -1198,7 +1198,7 @@ findIncDecBefore(MachineBasicBlock::iterator MBBI, unsigned Reg, // Skip debug values. MachineBasicBlock::iterator PrevMBBI = std::prev(MBBI); - while (PrevMBBI->isDebugValue() && PrevMBBI != BeginMBBI) + while (PrevMBBI->isDebugInstr() && PrevMBBI != BeginMBBI) --PrevMBBI; Offset = isIncrementOrDecrement(*PrevMBBI, Reg, Pred, PredReg); @@ -1214,7 +1214,7 @@ findIncDecAfter(MachineBasicBlock::iterator MBBI, unsigned Reg, MachineBasicBlock::iterator EndMBBI = MBB.end(); MachineBasicBlock::iterator NextMBBI = std::next(MBBI); // Skip debug values. - while (NextMBBI != EndMBBI && NextMBBI->isDebugValue()) + while (NextMBBI != EndMBBI && NextMBBI->isDebugInstr()) ++NextMBBI; if (NextMBBI == EndMBBI) return EndMBBI; @@ -1807,7 +1807,7 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) { MBBI = I; --Position; // Fallthrough to look into existing chain. - } else if (MBBI->isDebugValue()) { + } else if (MBBI->isDebugInstr()) { continue; } else if (MBBI->getOpcode() == ARM::t2LDRDi8 || MBBI->getOpcode() == ARM::t2STRDi8) { @@ -1891,8 +1891,8 @@ bool ARMLoadStoreOpt::MergeReturnIntoLDM(MachineBasicBlock &MBB) { MBBI->getOpcode() == ARM::tBX_RET || MBBI->getOpcode() == ARM::MOVPCLR)) { MachineBasicBlock::iterator PrevI = std::prev(MBBI); - // Ignore any DBG_VALUE instructions. - while (PrevI->isDebugValue() && PrevI != MBB.begin()) + // Ignore any debug instructions. + while (PrevI->isDebugInstr() && PrevI != MBB.begin()) --PrevI; MachineInstr &PrevMI = *PrevI; unsigned Opcode = PrevMI.getOpcode(); @@ -2063,7 +2063,7 @@ static bool IsSafeAndProfitableToMove(bool isLd, unsigned Base, // Are there stores / loads / calls between them? SmallSet<unsigned, 4> AddedRegPressure; while (++I != E) { - if (I->isDebugValue() || MemOps.count(&*I)) + if (I->isDebugInstr() || MemOps.count(&*I)) continue; if (I->isCall() || I->isTerminator() || I->hasUnmodeledSideEffects()) return false; @@ -2253,7 +2253,7 @@ bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB, // This is the new location for the loads / stores. MachineBasicBlock::iterator InsertPos = isLd ? FirstOp : LastOp; while (InsertPos != MBB->end() && - (MemOps.count(&*InsertPos) || InsertPos->isDebugValue())) + (MemOps.count(&*InsertPos) || InsertPos->isDebugInstr())) ++InsertPos; // If we are moving a pair of loads / stores, see if it makes sense @@ -2355,7 +2355,7 @@ ARMPreAllocLoadStoreOpt::RescheduleLoadStoreInstrs(MachineBasicBlock *MBB) { break; } - if (!MI.isDebugValue()) + if (!MI.isDebugInstr()) MI2LocMap[&MI] = ++Loc; if (!isMemoryOp(MI)) diff --git a/lib/Target/ARM/Thumb2ITBlockPass.cpp b/lib/Target/ARM/Thumb2ITBlockPass.cpp index 04bdd91b53e..e0a5f7f04fa 100644 --- a/lib/Target/ARM/Thumb2ITBlockPass.cpp +++ b/lib/Target/ARM/Thumb2ITBlockPass.cpp @@ -183,7 +183,7 @@ Thumb2ITBlockPass::MoveCopyOutOfITBlock(MachineInstr *MI, // If not, then there is nothing to be gained by moving the copy. MachineBasicBlock::iterator I = MI; ++I; MachineBasicBlock::iterator E = MI->getParent()->end(); - while (I != E && I->isDebugValue()) + while (I != E && I->isDebugInstr()) ++I; if (I != E) { unsigned NPredReg = 0; @@ -237,7 +237,7 @@ bool Thumb2ITBlockPass::InsertITInstructions(MachineBasicBlock &MBB) { // block so check the instruction we just put in the block. for (; MBBI != E && Pos && (!MI->isBranch() && !MI->isReturn()) ; ++MBBI) { - if (MBBI->isDebugValue()) + if (MBBI->isDebugInstr()) continue; MachineInstr *NMI = &*MBBI; diff --git a/lib/Target/ARM/Thumb2InstrInfo.cpp b/lib/Target/ARM/Thumb2InstrInfo.cpp index 179f1133d6e..d5f0ba9ee48 100644 --- a/lib/Target/ARM/Thumb2InstrInfo.cpp +++ b/lib/Target/ARM/Thumb2InstrInfo.cpp @@ -82,7 +82,7 @@ Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock::iterator E = MBB->begin(); unsigned Count = 4; // At most 4 instructions in an IT block. while (Count && MBBI != E) { - if (MBBI->isDebugValue()) { + if (MBBI->isDebugInstr()) { --MBBI; continue; } @@ -109,7 +109,7 @@ Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, bool Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const { - while (MBBI->isDebugValue()) { + while (MBBI->isDebugInstr()) { ++MBBI; if (MBBI == MBB.end()) return false; diff --git a/lib/Target/ARM/Thumb2SizeReduction.cpp b/lib/Target/ARM/Thumb2SizeReduction.cpp index 5357e26856e..115ba65ff86 100644 --- a/lib/Target/ARM/Thumb2SizeReduction.cpp +++ b/lib/Target/ARM/Thumb2SizeReduction.cpp @@ -1033,7 +1033,7 @@ bool Thumb2SizeReduce::ReduceMBB(MachineBasicBlock &MBB) { BundleMI = MI; continue; } - if (MI->isDebugValue()) + if (MI->isDebugInstr()) continue; LiveCPSR = UpdateCPSRUse(*MI, LiveCPSR); diff --git a/lib/Target/ARM/ThumbRegisterInfo.cpp b/lib/Target/ARM/ThumbRegisterInfo.cpp index 5e0818bea1c..e4bdd40fb74 100644 --- a/lib/Target/ARM/ThumbRegisterInfo.cpp +++ b/lib/Target/ARM/ThumbRegisterInfo.cpp @@ -475,7 +475,7 @@ bool ThumbRegisterInfo::saveScavengerRegister( // before that instead and adjust the UseMI. bool done = false; for (MachineBasicBlock::iterator II = I; !done && II != UseMI ; ++II) { - if (II->isDebugValue()) + if (II->isDebugInstr()) continue; // If this instruction affects R12, adjust our restore point. for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) { diff --git a/lib/Target/AVR/AVRInstrInfo.cpp b/lib/Target/AVR/AVRInstrInfo.cpp index 1a89a13693e..0c32334167f 100644 --- a/lib/Target/AVR/AVRInstrInfo.cpp +++ b/lib/Target/AVR/AVRInstrInfo.cpp @@ -273,7 +273,7 @@ bool AVRInstrInfo::analyzeBranch(MachineBasicBlock &MBB, while (I != MBB.begin()) { --I; - if (I->isDebugValue()) { + if (I->isDebugInstr()) { continue; } @@ -444,7 +444,7 @@ unsigned AVRInstrInfo::removeBranch(MachineBasicBlock &MBB, while (I != MBB.begin()) { --I; - if (I->isDebugValue()) { + if (I->isDebugInstr()) { continue; } //:TODO: add here the missing jmp instructions once they are implemented diff --git a/lib/Target/BPF/BPFInstrInfo.cpp b/lib/Target/BPF/BPFInstrInfo.cpp index ffb7acd222b..ab6d7c84cd1 100644 --- a/lib/Target/BPF/BPFInstrInfo.cpp +++ b/lib/Target/BPF/BPFInstrInfo.cpp @@ -93,7 +93,7 @@ bool BPFInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock::iterator I = MBB.end(); while (I != MBB.begin()) { --I; - if (I->isDebugValue()) + if (I->isDebugInstr()) continue; // Working from the bottom, when we see a non-terminator @@ -168,7 +168,7 @@ unsigned BPFInstrInfo::removeBranch(MachineBasicBlock &MBB, while (I != MBB.begin()) { --I; - if (I->isDebugValue()) + if (I->isDebugInstr()) continue; if (I->getOpcode() != BPF::JMP) break; diff --git a/lib/Target/Hexagon/BitTracker.cpp b/lib/Target/Hexagon/BitTracker.cpp index 378aafbc8dd..69529b0d116 100644 --- a/lib/Target/Hexagon/BitTracker.cpp +++ b/lib/Target/Hexagon/BitTracker.cpp @@ -843,7 +843,7 @@ void BT::visitPHI(const MachineInstr &PI) { void BT::visitNonBranch(const MachineInstr &MI) { if (Trace) dbgs() << "Visit MI(" << printMBBReference(*MI.getParent()) << "): " << MI; - if (MI.isDebugValue()) + if (MI.isDebugInstr()) return; assert(!MI.isBranch() && "Unexpected branch instruction"); diff --git a/lib/Target/Hexagon/HexagonAsmPrinter.cpp b/lib/Target/Hexagon/HexagonAsmPrinter.cpp index 6b836e29715..0ac83ea7c5f 100644 --- a/lib/Target/Hexagon/HexagonAsmPrinter.cpp +++ b/lib/Target/Hexagon/HexagonAsmPrinter.cpp @@ -760,7 +760,7 @@ void HexagonAsmPrinter::EmitInstruction(const MachineInstr *MI) { MachineBasicBlock::const_instr_iterator MII = MI->getIterator(); for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII) - if (!MII->isDebugValue() && !MII->isImplicitDef()) + if (!MII->isDebugInstr() && !MII->isImplicitDef()) HexagonLowerToMC(MCII, &*MII, MCB, *this); } else { HexagonLowerToMC(MCII, MI, MCB, *this); diff --git a/lib/Target/Hexagon/HexagonBlockRanges.cpp b/lib/Target/Hexagon/HexagonBlockRanges.cpp index 8153c49447d..2fb30dfbc1c 100644 --- a/lib/Target/Hexagon/HexagonBlockRanges.cpp +++ b/lib/Target/Hexagon/HexagonBlockRanges.cpp @@ -160,7 +160,7 @@ HexagonBlockRanges::InstrIndexMap::InstrIndexMap(MachineBasicBlock &B) IndexType Idx = IndexType::First; First = Idx; for (auto &In : B) { - if (In.isDebugValue()) + if (In.isDebugInstr()) continue; assert(getIndex(&In) == IndexType::None && "Instruction already in map"); Map.insert(std::make_pair(Idx, &In)); @@ -314,7 +314,7 @@ void HexagonBlockRanges::computeInitialLiveRanges(InstrIndexMap &IndexMap, RegisterSet Defs, Clobbers; for (auto &In : B) { - if (In.isDebugValue()) + if (In.isDebugInstr()) continue; IndexType Index = IndexMap.getIndex(&In); // Process uses first. diff --git a/lib/Target/Hexagon/HexagonConstPropagation.cpp b/lib/Target/Hexagon/HexagonConstPropagation.cpp index 62b2e892b70..730cfafae42 100644 --- a/lib/Target/Hexagon/HexagonConstPropagation.cpp +++ b/lib/Target/Hexagon/HexagonConstPropagation.cpp @@ -799,7 +799,7 @@ bool MachineConstPropagator::computeBlockSuccessors(const MachineBasicBlock *MB, SetVector<const MachineBasicBlock*> &Targets) { MachineBasicBlock::const_iterator FirstBr = MB->end(); for (const MachineInstr &MI : *MB) { - if (MI.isDebugValue()) + if (MI.isDebugInstr()) continue; if (MI.isBranch()) { FirstBr = MI.getIterator(); @@ -814,7 +814,7 @@ bool MachineConstPropagator::computeBlockSuccessors(const MachineBasicBlock *MB, for (MachineBasicBlock::const_iterator I = FirstBr; I != End; ++I) { const MachineInstr &MI = *I; // Can there be debug instructions between branches? - if (MI.isDebugValue()) + if (MI.isDebugInstr()) continue; if (!InstrExec.count(&MI)) continue; @@ -896,7 +896,7 @@ void MachineConstPropagator::propagate(MachineFunction &MF) { // If the successor block just became executable, visit all instructions. // To see if this is the first time we're visiting it, check the first // non-debug instruction to see if it is executable. - while (It != End && It->isDebugValue()) + while (It != End && It->isDebugInstr()) ++It; assert(It == End || !It->isPHI()); // If this block has been visited, go on to the next one. @@ -905,7 +905,7 @@ void MachineConstPropagator::propagate(MachineFunction &MF) { // For now, scan all non-branch instructions. Branches require different // processing. while (It != End && !It->isBranch()) { - if (!It->isDebugValue()) { + if (!It->isDebugInstr()) { InstrExec.insert(&*It); visitNonBranch(*It); } diff --git a/lib/Target/Hexagon/HexagonCopyToCombine.cpp b/lib/Target/Hexagon/HexagonCopyToCombine.cpp index 087a77203fc..f3d24739da4 100644 --- a/lib/Target/Hexagon/HexagonCopyToCombine.cpp +++ b/lib/Target/Hexagon/HexagonCopyToCombine.cpp @@ -300,7 +300,7 @@ bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr &I1, // * reads I2's def reg // * or has unmodelled side effects // we can't move I2 across it. - if (I->isDebugValue()) + if (I->isDebugInstr()) continue; if (isUnsafeToMoveAcross(*I, I2UseReg, I2DestReg, TRI)) { @@ -358,7 +358,7 @@ bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr &I1, // to remove the implicit killed %d4 operand. For now, we are // conservative and disallow the move. // we can't move I1 across it. - if (MI.isDebugValue()) { + if (MI.isDebugInstr()) { if (MI.readsRegister(I1DestReg, TRI)) // Move this instruction after I2. DbgMItoMove.push_back(&MI); continue; @@ -396,7 +396,7 @@ void HexagonCopyToCombine::findPotentialNewifiableTFRs(MachineBasicBlock &BB) { DenseMap<unsigned, MachineInstr *> LastDef; for (MachineInstr &MI : BB) { - if (MI.isDebugValue()) + if (MI.isDebugInstr()) continue; // Mark TFRs that feed a potential new value store as such. @@ -423,7 +423,7 @@ HexagonCopyToCombine::findPotentialNewifiableTFRs(MachineBasicBlock &BB) { MachineBasicBlock::iterator It(DefInst); unsigned NumInstsToDef = 0; while (&*It != &MI) { - if (!It->isDebugValue()) + if (!It->isDebugInstr()) ++NumInstsToDef; ++It; } @@ -489,7 +489,7 @@ bool HexagonCopyToCombine::runOnMachineFunction(MachineFunction &MF) { MI != End;) { MachineInstr &I1 = *MI++; - if (I1.isDebugValue()) + if (I1.isDebugInstr()) continue; // Don't combine a TFR whose user could be newified (instructions that @@ -526,7 +526,7 @@ MachineInstr *HexagonCopyToCombine::findPairable(MachineInstr &I1, bool &DoInsertAtI1, bool AllowC64) { MachineBasicBlock::iterator I2 = std::next(MachineBasicBlock::iterator(I1)); - while (I2 != I1.getParent()->end() && I2->isDebugValue()) + while (I2 != I1.getParent()->end() && I2->isDebugInstr()) ++I2; unsigned I1DestReg = I1.getOperand(0).getReg(); diff --git a/lib/Target/Hexagon/HexagonEarlyIfConv.cpp b/lib/Target/Hexagon/HexagonEarlyIfConv.cpp index 660466d0d6c..bbd06ff747e 100644 --- a/lib/Target/Hexagon/HexagonEarlyIfConv.cpp +++ b/lib/Target/Hexagon/HexagonEarlyIfConv.cpp @@ -367,7 +367,7 @@ bool HexagonEarlyIfConversion::isValidCandidate(const MachineBasicBlock *B) return false; for (auto &MI : *B) { - if (MI.isDebugValue()) + if (MI.isDebugInstr()) continue; if (MI.isConditionalBranch()) return false; diff --git a/lib/Target/Hexagon/HexagonGenMux.cpp b/lib/Target/Hexagon/HexagonGenMux.cpp index 7c91412c250..e5af96468af 100644 --- a/lib/Target/Hexagon/HexagonGenMux.cpp +++ b/lib/Target/Hexagon/HexagonGenMux.cpp @@ -356,7 +356,7 @@ bool HexagonGenMux::genMuxInBlock(MachineBasicBlock &B) { return false; }; for (auto I = B.rbegin(), E = B.rend(); I != E; ++I) { - if (I->isDebugValue()) + if (I->isDebugInstr()) continue; // This isn't 100% accurate, but it's safe. // It won't detect (as a kill) a case like this diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp index 78e82579c47..1ec1ce01336 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -134,7 +134,7 @@ static unsigned nonDbgMICount(MachineBasicBlock::const_instr_iterator MIB, MachineBasicBlock::const_instr_iterator MIE) { unsigned Count = 0; for (; MIB != MIE; ++MIB) { - if (!MIB->isDebugValue()) + if (!MIB->isDebugInstr()) ++Count; } return Count; @@ -419,7 +419,7 @@ bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB, I = MBB.instr_end(); --I; - while (I->isDebugValue()) { + while (I->isDebugInstr()) { if (I == MBB.instr_begin()) return false; --I; @@ -562,7 +562,7 @@ unsigned HexagonInstrInfo::removeBranch(MachineBasicBlock &MBB, unsigned Count = 0; while (I != MBB.begin()) { --I; - if (I->isDebugValue()) + if (I->isDebugInstr()) continue; // Only removing branches from end of MBB. if (!I->isBranch()) @@ -1626,7 +1626,7 @@ bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr &MI, // considered a scheduling hazard, which is wrong. It should be the actual // instruction preceding the dbg_value instruction(s), just like it is // when debug info is not present. - if (MI.isDebugValue()) + if (MI.isDebugInstr()) return false; // Throwing call is a boundary. @@ -3164,7 +3164,7 @@ SmallVector<MachineInstr*, 2> HexagonInstrInfo::getBranchingInstrs( I = MBB.instr_end(); --I; - while (I->isDebugValue()) { + while (I->isDebugInstr()) { if (I == MBB.instr_begin()) return Jumpers; --I; @@ -4201,7 +4201,7 @@ short HexagonInstrInfo::getRegForm(const MachineInstr &MI) const { // use a constant extender, which requires another 4 bytes. // For debug instructions and prolog labels, return 0. unsigned HexagonInstrInfo::getSize(const MachineInstr &MI) const { - if (MI.isDebugValue() || MI.isPosition()) + if (MI.isDebugInstr() || MI.isPosition()) return 0; unsigned Size = MI.getDesc().getSize(); diff --git a/lib/Target/Hexagon/HexagonNewValueJump.cpp b/lib/Target/Hexagon/HexagonNewValueJump.cpp index a3686c89d61..3dace168284 100644 --- a/lib/Target/Hexagon/HexagonNewValueJump.cpp +++ b/lib/Target/Hexagon/HexagonNewValueJump.cpp @@ -302,7 +302,7 @@ static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII, // and satisfy the following conditions. ++II; for (MachineBasicBlock::iterator localII = II; localII != end; ++localII) { - if (localII->isDebugValue()) + if (localII->isDebugInstr()) continue; // Check 1. @@ -494,7 +494,7 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) { for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin(); MII != E;) { MachineInstr &MI = *--MII; - if (MI.isDebugValue()) { + if (MI.isDebugInstr()) { continue; } diff --git a/lib/Target/Hexagon/HexagonSplitDouble.cpp b/lib/Target/Hexagon/HexagonSplitDouble.cpp index 4979ce1e7d6..386e6cbad1f 100644 --- a/lib/Target/Hexagon/HexagonSplitDouble.cpp +++ b/lib/Target/Hexagon/HexagonSplitDouble.cpp @@ -163,7 +163,7 @@ bool HexagonSplitDoubleRegs::isFixedInstr(const MachineInstr *MI) const { if (MI->mayLoad() || MI->mayStore()) if (MemRefsFixed || isVolatileInstr(MI)) return true; - if (MI->isDebugValue()) + if (MI->isDebugInstr()) return false; unsigned Opc = MI->getOpcode(); diff --git a/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp index 8c528b9ed22..2ae48e3d68f 100644 --- a/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ b/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -1037,7 +1037,7 @@ void HexagonPacketizerList::initPacketizerState() { // Ignore bundling of pseudo instructions. bool HexagonPacketizerList::ignorePseudoInstruction(const MachineInstr &MI, const MachineBasicBlock *) { - if (MI.isDebugValue()) + if (MI.isDebugInstr()) return true; if (MI.isCFIInstruction()) diff --git a/lib/Target/Hexagon/RDFGraph.cpp b/lib/Target/Hexagon/RDFGraph.cpp index ceb4887a36d..3d1ec31dada 100644 --- a/lib/Target/Hexagon/RDFGraph.cpp +++ b/lib/Target/Hexagon/RDFGraph.cpp @@ -893,7 +893,7 @@ void DataFlowGraph::build(unsigned Options) { NodeAddr<BlockNode*> BA = newBlock(Func, &B); BlockNodes.insert(std::make_pair(&B, BA)); for (MachineInstr &I : B) { - if (I.isDebugValue()) + if (I.isDebugInstr()) continue; buildStmt(BA, I); } diff --git a/lib/Target/Hexagon/RDFLiveness.cpp b/lib/Target/Hexagon/RDFLiveness.cpp index ef50a5319dc..c257d754ddf 100644 --- a/lib/Target/Hexagon/RDFLiveness.cpp +++ b/lib/Target/Hexagon/RDFLiveness.cpp @@ -880,7 +880,7 @@ void Liveness::resetKills(MachineBasicBlock *B) { for (auto I = B->rbegin(), E = B->rend(); I != E; ++I) { MachineInstr *MI = &*I; - if (MI->isDebugValue()) + if (MI->isDebugInstr()) continue; MI->clearKillInfo(); diff --git a/lib/Target/Lanai/LanaiDelaySlotFiller.cpp b/lib/Target/Lanai/LanaiDelaySlotFiller.cpp index 6b4fa777178..ea76a112837 100644 --- a/lib/Target/Lanai/LanaiDelaySlotFiller.cpp +++ b/lib/Target/Lanai/LanaiDelaySlotFiller.cpp @@ -156,7 +156,7 @@ bool Filler::findDelayInstr(MachineBasicBlock &MBB, for (MachineBasicBlock::reverse_instr_iterator I = ++Slot.getReverse(); I != MBB.instr_rend(); ++I) { // skip debug value - if (I->isDebugValue()) + if (I->isDebugInstr()) continue; // Convert to forward iterator. diff --git a/lib/Target/Lanai/LanaiInstrInfo.cpp b/lib/Target/Lanai/LanaiInstrInfo.cpp index a7c9a7a7f28..493d02bef37 100644 --- a/lib/Target/Lanai/LanaiInstrInfo.cpp +++ b/lib/Target/Lanai/LanaiInstrInfo.cpp @@ -573,8 +573,8 @@ bool LanaiInstrInfo::analyzeBranch(MachineBasicBlock &MBB, while (Instruction != MBB.begin()) { --Instruction; - // Skip over debug values. - if (Instruction->isDebugValue()) + // Skip over debug instructions. + if (Instruction->isDebugInstr()) continue; // Working from the bottom, when we see a non-terminator @@ -699,7 +699,7 @@ unsigned LanaiInstrInfo::removeBranch(MachineBasicBlock &MBB, while (Instruction != MBB.begin()) { --Instruction; - if (Instruction->isDebugValue()) + if (Instruction->isDebugInstr()) continue; if (Instruction->getOpcode() != Lanai::BT && Instruction->getOpcode() != Lanai::BRCC) { diff --git a/lib/Target/Lanai/LanaiMemAluCombiner.cpp b/lib/Target/Lanai/LanaiMemAluCombiner.cpp index c29c933db74..35e2542dfb1 100644 --- a/lib/Target/Lanai/LanaiMemAluCombiner.cpp +++ b/lib/Target/Lanai/LanaiMemAluCombiner.cpp @@ -343,7 +343,7 @@ MbbIterator LanaiMemAluCombiner::findClosestSuitableAluInstr( break; // Skip over debug instructions - if (First->isDebugValue()) + if (First->isDebugInstr()) continue; if (isSuitableAluInstr(IsSpls, First, *Base, *Offset)) { diff --git a/lib/Target/MSP430/MSP430InstrInfo.cpp b/lib/Target/MSP430/MSP430InstrInfo.cpp index 6135ce08092..dd1b30a3e47 100644 --- a/lib/Target/MSP430/MSP430InstrInfo.cpp +++ b/lib/Target/MSP430/MSP430InstrInfo.cpp @@ -113,7 +113,7 @@ unsigned MSP430InstrInfo::removeBranch(MachineBasicBlock &MBB, while (I != MBB.begin()) { --I; - if (I->isDebugValue()) + if (I->isDebugInstr()) continue; if (I->getOpcode() != MSP430::JMP && I->getOpcode() != MSP430::JCC && @@ -183,7 +183,7 @@ bool MSP430InstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock::iterator I = MBB.end(); while (I != MBB.begin()) { --I; - if (I->isDebugValue()) + if (I->isDebugInstr()) continue; // Working from the bottom, when we see a non-terminator diff --git a/lib/Target/Mips/MipsAsmPrinter.cpp b/lib/Target/Mips/MipsAsmPrinter.cpp index 97bb5fbdf95..8ffc0731abc 100644 --- a/lib/Target/Mips/MipsAsmPrinter.cpp +++ b/lib/Target/Mips/MipsAsmPrinter.cpp @@ -160,6 +160,8 @@ void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) { PrintDebugValueComment(MI, OS); return; } + if (MI->isDebugLabel()) + return; // If we just ended a constant pool, mark it as such. if (InConstantPool && Opc != Mips::CONSTPOOL_ENTRY) { diff --git a/lib/Target/Mips/MipsConstantIslandPass.cpp b/lib/Target/Mips/MipsConstantIslandPass.cpp index 5e7a1afc66f..5ee816be373 100644 --- a/lib/Target/Mips/MipsConstantIslandPass.cpp +++ b/lib/Target/Mips/MipsConstantIslandPass.cpp @@ -661,7 +661,7 @@ initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs) { if (!BBHasFallthrough(&MBB)) WaterList.push_back(&MBB); for (MachineInstr &MI : MBB) { - if (MI.isDebugValue()) + if (MI.isDebugInstr()) continue; int Opc = MI.getOpcode(); diff --git a/lib/Target/Mips/MipsDelaySlotFiller.cpp b/lib/Target/Mips/MipsDelaySlotFiller.cpp index 4f292e66ce0..dfebc343d84 100644 --- a/lib/Target/Mips/MipsDelaySlotFiller.cpp +++ b/lib/Target/Mips/MipsDelaySlotFiller.cpp @@ -679,7 +679,7 @@ bool Filler::searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End, ++I; // skip debug value - if (CurrI->isDebugValue()) + if (CurrI->isDebugInstr()) continue; if (terminateSearch(*CurrI)) diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp index 947d7e45a9f..9254ae6a13b 100644 --- a/lib/Target/Mips/MipsInstrInfo.cpp +++ b/lib/Target/Mips/MipsInstrInfo.cpp @@ -163,7 +163,7 @@ unsigned MipsInstrInfo::removeBranch(MachineBasicBlock &MBB, // Note that indirect branches are not removed. while (I != REnd && removed < 2) { // Skip past debug instructions. - if (I->isDebugValue()) { + if (I->isDebugInstr()) { ++I; continue; } @@ -195,7 +195,7 @@ MipsInstrInfo::BranchType MipsInstrInfo::analyzeBranch( MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend(); // Skip all the debug instructions. - while (I != REnd && I->isDebugValue()) + while (I != REnd && I->isDebugInstr()) ++I; if (I == REnd || !isUnpredicatedTerminator(*I)) { @@ -220,7 +220,7 @@ MipsInstrInfo::BranchType MipsInstrInfo::analyzeBranch( // Skip past any debug instruction to see if the second last actual // is a branch. ++I; - while (I != REnd && I->isDebugValue()) + while (I != REnd && I->isDebugInstr()) ++I; if (I != REnd) { diff --git a/lib/Target/Mips/MipsLongBranch.cpp b/lib/Target/Mips/MipsLongBranch.cpp index bc5f0df211e..7a7c8abfc6f 100644 --- a/lib/Target/Mips/MipsLongBranch.cpp +++ b/lib/Target/Mips/MipsLongBranch.cpp @@ -125,7 +125,7 @@ static MachineBasicBlock *getTargetMBB(const MachineInstr &Br) { // found or it reaches E. static ReverseIter getNonDebugInstr(ReverseIter B, const ReverseIter &E) { for (; B != E; ++B) - if (!B->isDebugValue()) + if (!B->isDebugInstr()) return B; return E; diff --git a/lib/Target/PowerPC/PPCEarlyReturn.cpp b/lib/Target/PowerPC/PPCEarlyReturn.cpp index 1699463c0a4..ed5e496b32f 100644 --- a/lib/Target/PowerPC/PPCEarlyReturn.cpp +++ b/lib/Target/PowerPC/PPCEarlyReturn.cpp @@ -128,7 +128,7 @@ protected: if (J->getOperand(i).isMBB() && J->getOperand(i).getMBB() == &ReturnMBB) OtherReference = true; - } else if (!J->isTerminator() && !J->isDebugValue()) + } else if (!J->isTerminator() && !J->isDebugInstr()) break; if (J == (*PI)->begin()) diff --git a/lib/Target/PowerPC/PPCHazardRecognizers.cpp b/lib/Target/PowerPC/PPCHazardRecognizers.cpp index f327396370f..4c718f8883e 100644 --- a/lib/Target/PowerPC/PPCHazardRecognizers.cpp +++ b/lib/Target/PowerPC/PPCHazardRecognizers.cpp @@ -330,7 +330,7 @@ getHazardType(SUnit *SU, int Stalls) { MachineInstr *MI = SU->getInstr(); - if (MI->isDebugValue()) + if (MI->isDebugInstr()) return NoHazard; unsigned Opcode = MI->getOpcode(); @@ -388,7 +388,7 @@ getHazardType(SUnit *SU, int Stalls) { void PPCHazardRecognizer970::EmitInstruction(SUnit *SU) { MachineInstr *MI = SU->getInstr(); - if (MI->isDebugValue()) + if (MI->isDebugInstr()) return; unsigned Opcode = MI->getOpcode(); diff --git a/lib/Target/PowerPC/PPCMIPeephole.cpp b/lib/Target/PowerPC/PPCMIPeephole.cpp index 8151e433d6a..6f44e3adcfe 100644 --- a/lib/Target/PowerPC/PPCMIPeephole.cpp +++ b/lib/Target/PowerPC/PPCMIPeephole.cpp @@ -232,7 +232,7 @@ bool PPCMIPeephole::simplifyCode(void) { SomethingChanged = false; for (MachineBasicBlock &MBB : *MF) { for (MachineInstr &MI : MBB) { - if (MI.isDebugValue()) + if (MI.isDebugInstr()) continue; if (TII->convertToImmediateForm(MI)) { @@ -261,7 +261,7 @@ bool PPCMIPeephole::simplifyCode(void) { } // Ignore debug instructions. - if (MI.isDebugValue()) + if (MI.isDebugInstr()) continue; // Per-opcode peepholes. diff --git a/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp b/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp index 635f8cd53ec..83c9dd67c33 100644 --- a/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp +++ b/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp @@ -249,7 +249,7 @@ bool PPCVSXSwapRemoval::gatherVectorInstructions() { for (MachineBasicBlock &MBB : *MF) { for (MachineInstr &MI : MBB) { - if (MI.isDebugValue()) + if (MI.isDebugInstr()) continue; bool RelevantInstr = false; diff --git a/lib/Target/Sparc/DelaySlotFiller.cpp b/lib/Target/Sparc/DelaySlotFiller.cpp index 9b1d0f5bf3c..6290e5a15a8 100644 --- a/lib/Target/Sparc/DelaySlotFiller.cpp +++ b/lib/Target/Sparc/DelaySlotFiller.cpp @@ -207,8 +207,8 @@ Filler::findDelayInstr(MachineBasicBlock &MBB, if (!done) --I; - // skip debug value - if (I->isDebugValue()) + // skip debug instruction + if (I->isDebugInstr()) continue; if (I->hasUnmodeledSideEffects() || I->isInlineAsm() || I->isPosition() || diff --git a/lib/Target/Sparc/SparcInstrInfo.cpp b/lib/Target/Sparc/SparcInstrInfo.cpp index ea8ed830baf..6750763d8ee 100644 --- a/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/lib/Target/Sparc/SparcInstrInfo.cpp @@ -280,7 +280,7 @@ unsigned SparcInstrInfo::removeBranch(MachineBasicBlock &MBB, while (I != MBB.begin()) { --I; - if (I->isDebugValue()) + if (I->isDebugInstr()) continue; if (I->getOpcode() != SP::BA diff --git a/lib/Target/SystemZ/SystemZInstrInfo.cpp b/lib/Target/SystemZ/SystemZInstrInfo.cpp index f094cf18dfd..f0f9211efd5 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.cpp +++ b/lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -389,7 +389,7 @@ bool SystemZInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock::iterator I = MBB.end(); while (I != MBB.begin()) { --I; - if (I->isDebugValue()) + if (I->isDebugInstr()) continue; // Working from the bottom, when we see a non-terminator instruction, we're @@ -479,7 +479,7 @@ unsigned SystemZInstrInfo::removeBranch(MachineBasicBlock &MBB, while (I != MBB.begin()) { --I; - if (I->isDebugValue()) + if (I->isDebugInstr()) continue; if (!I->isBranch()) break; diff --git a/lib/Target/SystemZ/SystemZLongBranch.cpp b/lib/Target/SystemZ/SystemZLongBranch.cpp index ef8b9806f89..802962bd4db 100644 --- a/lib/Target/SystemZ/SystemZLongBranch.cpp +++ b/lib/Target/SystemZ/SystemZLongBranch.cpp @@ -295,7 +295,7 @@ uint64_t SystemZLongBranch::initMBBInfo() { // Add the terminators. while (MI != End) { - if (!MI->isDebugValue()) { + if (!MI->isDebugInstr()) { assert(MI->isTerminator() && "Terminator followed by non-terminator"); Terminators.push_back(describeTerminator(*MI)); skipTerminator(Position, Terminators.back(), false); diff --git a/lib/Target/SystemZ/SystemZMachineScheduler.cpp b/lib/Target/SystemZ/SystemZMachineScheduler.cpp index 51e8beb085a..1de11a1166d 100644 --- a/lib/Target/SystemZ/SystemZMachineScheduler.cpp +++ b/lib/Target/SystemZ/SystemZMachineScheduler.cpp @@ -65,7 +65,7 @@ advanceTo(MachineBasicBlock::iterator NextBegin) { std::next(LastEmittedMI) : MBB->begin()); for (; I != NextBegin; ++I) { - if (I->isPosition() || I->isDebugValue()) + if (I->isPosition() || I->isDebugInstr()) continue; HazardRec->emitInstruction(&*I); } diff --git a/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp b/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp index cf1bbfa5e18..3429c4fc6e2 100644 --- a/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp +++ b/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp @@ -265,7 +265,7 @@ static void FixEndsAtEndOfFunction( for (MachineBasicBlock &MBB : reverse(MF)) { for (MachineInstr &MI : reverse(MBB)) { - if (MI.isPosition() || MI.isDebugValue()) + if (MI.isPosition() || MI.isDebugInstr()) continue; if (MI.getOpcode() == WebAssembly::END_BLOCK) { BlockTops[&MI]->getOperand(0).setImm(int32_t(retType)); diff --git a/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp b/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp index cf14643627a..caf12a610be 100644 --- a/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp +++ b/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp @@ -231,7 +231,7 @@ bool WebAssemblyExplicitLocals::runOnMachineFunction(MachineFunction &MF) { MachineInstr &MI = *I++; assert(!WebAssembly::isArgument(MI)); - if (MI.isDebugValue() || MI.isLabel()) + if (MI.isDebugInstr() || MI.isLabel()) continue; // Replace tee instructions with tee_local. The difference is that tee @@ -375,7 +375,7 @@ bool WebAssemblyExplicitLocals::runOnMachineFunction(MachineFunction &MF) { // Assert that all registers have been stackified at this point. for (const MachineBasicBlock &MBB : MF) { for (const MachineInstr &MI : MBB) { - if (MI.isDebugValue() || MI.isLabel()) + if (MI.isDebugInstr() || MI.isLabel()) continue; for (const MachineOperand &MO : MI.explicit_operands()) { assert( diff --git a/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp b/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp index 739d6cf6253..fbdf4c011a9 100644 --- a/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp +++ b/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp @@ -151,7 +151,7 @@ unsigned WebAssemblyInstrInfo::removeBranch(MachineBasicBlock &MBB, while (I != MBB.instr_begin()) { --I; - if (I->isDebugValue()) + if (I->isDebugInstr()) continue; if (!I->isTerminator()) break; diff --git a/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp b/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp index 6780f252902..c326bdb8a7b 100644 --- a/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp +++ b/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp @@ -163,7 +163,7 @@ static void Query(const MachineInstr &MI, AliasAnalysis &AA, bool &Read, assert(!MI.isPosition()); assert(!MI.isTerminator()); - if (MI.isDebugValue()) + if (MI.isDebugInstr()) return; // Check for loads. @@ -871,7 +871,7 @@ bool WebAssemblyRegStackify::runOnMachineFunction(MachineFunction &MF) { SmallVector<unsigned, 0> Stack; for (MachineBasicBlock &MBB : MF) { for (MachineInstr &MI : MBB) { - if (MI.isDebugValue()) + if (MI.isDebugInstr()) continue; for (MachineOperand &MO : reverse(MI.explicit_operands())) { if (!MO.isReg()) diff --git a/lib/Target/X86/X86CallFrameOptimization.cpp b/lib/Target/X86/X86CallFrameOptimization.cpp index 522dc7926b9..c73fd6eb144 100644 --- a/lib/Target/X86/X86CallFrameOptimization.cpp +++ b/lib/Target/X86/X86CallFrameOptimization.cpp @@ -375,7 +375,7 @@ void X86CallFrameOptimization::collectCallInfo(MachineFunction &MF, // Skip over DEBUG_VALUE. // For globals in PIC mode, we can have some LEAs here. Skip them as well. // TODO: Extend this to something that covers more cases. - while (I->getOpcode() == X86::LEA32r || I->isDebugValue()) + while (I->getOpcode() == X86::LEA32r || I->isDebugInstr()) ++I; unsigned StackPtr = RegInfo.getStackRegister(); diff --git a/lib/Target/X86/X86CmovConversion.cpp b/lib/Target/X86/X86CmovConversion.cpp index 493d42c85b4..38baa90f479 100644 --- a/lib/Target/X86/X86CmovConversion.cpp +++ b/lib/Target/X86/X86CmovConversion.cpp @@ -295,7 +295,7 @@ bool X86CmovConverterPass::collectCmovCandidates( for (auto &I : *MBB) { // Skip debug instructions. - if (I.isDebugValue()) + if (I.isDebugInstr()) continue; X86::CondCode CC = X86::getCondFromCMovOpc(I.getOpcode()); // Check if we found a X86::CMOVrr instruction. @@ -435,7 +435,7 @@ bool X86CmovConverterPass::checkForProfitableCmovCandidates( RegDefMaps[PhyRegType].clear(); for (MachineInstr &MI : *MBB) { // Skip debug instructions. - if (MI.isDebugValue()) + if (MI.isDebugInstr()) continue; unsigned MIDepth = 0; unsigned MIDepthOpt = 0; @@ -605,7 +605,7 @@ static void packCmovGroup(MachineInstr *First, MachineInstr *Last) { SmallVector<MachineInstr *, 2> DBGInstructions; for (auto I = First->getIterator(), E = Last->getIterator(); I != E; I++) { - if (I->isDebugValue()) + if (I->isDebugInstr()) DBGInstructions.push_back(&*I); } diff --git a/lib/Target/X86/X86FloatingPoint.cpp b/lib/Target/X86/X86FloatingPoint.cpp index 248f9607c63..ffdb949918f 100644 --- a/lib/Target/X86/X86FloatingPoint.cpp +++ b/lib/Target/X86/X86FloatingPoint.cpp @@ -1675,7 +1675,7 @@ void FPS::setKillFlags(MachineBasicBlock &MBB) const { for (MachineBasicBlock::reverse_iterator I = MBB.rbegin(), E = MBB.rend(); I != E; ++I) { - if (I->isDebugValue()) + if (I->isDebugInstr()) continue; std::bitset<8> Defs; diff --git a/lib/Target/X86/X86FrameLowering.cpp b/lib/Target/X86/X86FrameLowering.cpp index 42f9676fbe9..18f62e06afa 100644 --- a/lib/Target/X86/X86FrameLowering.cpp +++ b/lib/Target/X86/X86FrameLowering.cpp @@ -3025,7 +3025,7 @@ void X86FrameLowering::orderFrameObjects( // Count the number of uses for each object. for (auto &MBB : MF) { for (auto &MI : MBB) { - if (MI.isDebugValue()) + if (MI.isDebugInstr()) continue; for (const MachineOperand &MO : MI.operands()) { // Check to see if it's a local stack symbol. diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 203c1318046..16ee56ecaa0 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -27766,7 +27766,7 @@ X86TargetLowering::EmitSjLjDispatchBlock(MachineInstr &MI, MCSymbol *Sym = nullptr; for (const auto &MI : MBB) { - if (MI.isDebugValue()) + if (MI.isDebugInstr()) continue; assert(MI.isEHLabel() && "expected EH_LABEL"); diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index 5c85c7e5282..31ce4bdc767 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -4340,8 +4340,8 @@ bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB, // This instruction defines EFLAGS, no need to look any further. return true; ++Iter; - // Skip over DBG_VALUE. - while (Iter != E && Iter->isDebugValue()) + // Skip over debug instructions. + while (Iter != E && Iter->isDebugInstr()) ++Iter; } @@ -4363,8 +4363,8 @@ bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB, return !MBB.isLiveIn(X86::EFLAGS); --Iter; - // Skip over DBG_VALUE. - while (Iter != B && Iter->isDebugValue()) + // Skip over debug instructions. + while (Iter != B && Iter->isDebugInstr()) --Iter; bool SawKill = false; @@ -6254,7 +6254,7 @@ void X86InstrInfo::replaceBranchWithTailCall( MachineBasicBlock::iterator I = MBB.end(); while (I != MBB.begin()) { --I; - if (I->isDebugValue()) + if (I->isDebugInstr()) continue; if (!I->isBranch()) assert(0 && "Can't find the branch to replace!"); @@ -6322,7 +6322,7 @@ bool X86InstrInfo::AnalyzeBranchImpl( MachineBasicBlock::iterator UnCondBrIter = MBB.end(); while (I != MBB.begin()) { --I; - if (I->isDebugValue()) + if (I->isDebugInstr()) continue; // Working from the bottom, when we see a non-terminator instruction, we're @@ -6559,7 +6559,7 @@ unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB, while (I != MBB.begin()) { --I; - if (I->isDebugValue()) + if (I->isDebugInstr()) continue; if (I->getOpcode() != X86::JMP_1 && X86::getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID) @@ -11172,7 +11172,7 @@ X86GenInstrInfo::MachineOutlinerInstrType X86InstrInfo::getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const { MachineInstr &MI = *MIT; // Don't allow debug values to impact outlining type. - if (MI.isDebugValue() || MI.isIndirectDebugValue()) + if (MI.isDebugInstr() || MI.isIndirectDebugValue()) return MachineOutlinerInstrType::Invisible; // At this point, KILL instructions don't really tell us much so we can go diff --git a/lib/Target/X86/X86PadShortFunction.cpp b/lib/Target/X86/X86PadShortFunction.cpp index 2fe5cb973da..85b9aecc210 100644 --- a/lib/Target/X86/X86PadShortFunction.cpp +++ b/lib/Target/X86/X86PadShortFunction.cpp @@ -129,7 +129,7 @@ bool PadShortFunc::runOnMachineFunction(MachineFunction &MF) { "Basic block should contain at least a RET but is empty"); MachineBasicBlock::iterator ReturnLoc = --MBB->end(); - while (ReturnLoc->isDebugValue()) + while (ReturnLoc->isDebugInstr()) --ReturnLoc; assert(ReturnLoc->isReturn() && !ReturnLoc->isCall() && "Basic block does not end with RET"); diff --git a/lib/Target/XCore/XCoreFrameLowering.cpp b/lib/Target/XCore/XCoreFrameLowering.cpp index a5fe63b2829..b87c149a36d 100644 --- a/lib/Target/XCore/XCoreFrameLowering.cpp +++ b/lib/Target/XCore/XCoreFrameLowering.cpp @@ -427,7 +427,7 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB, bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(*MF); DebugLoc DL; - if (MI != MBB.end() && !MI->isDebugValue()) + if (MI != MBB.end() && !MI->isDebugInstr()) DL = MI->getDebugLoc(); for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin(); diff --git a/lib/Target/XCore/XCoreInstrInfo.cpp b/lib/Target/XCore/XCoreInstrInfo.cpp index c885332b07a..d5e276788f7 100644 --- a/lib/Target/XCore/XCoreInstrInfo.cpp +++ b/lib/Target/XCore/XCoreInstrInfo.cpp @@ -364,7 +364,7 @@ void XCoreInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, const TargetRegisterInfo *TRI) const { DebugLoc DL; - if (I != MBB.end() && !I->isDebugValue()) + if (I != MBB.end() && !I->isDebugInstr()) DL = I->getDebugLoc(); MachineFunction *MF = MBB.getParent(); const MachineFrameInfo &MFI = MF->getFrameInfo(); @@ -386,7 +386,7 @@ void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, const TargetRegisterInfo *TRI) const { DebugLoc DL; - if (I != MBB.end() && !I->isDebugValue()) + if (I != MBB.end() && !I->isDebugInstr()) DL = I->getDebugLoc(); MachineFunction *MF = MBB.getParent(); const MachineFrameInfo &MFI = MF->getFrameInfo(); @@ -429,7 +429,7 @@ MachineBasicBlock::iterator XCoreInstrInfo::loadImmediate( MachineBasicBlock::iterator MI, unsigned Reg, uint64_t Value) const { DebugLoc dl; - if (MI != MBB.end() && !MI->isDebugValue()) + if (MI != MBB.end() && !MI->isDebugInstr()) dl = MI->getDebugLoc(); if (isImmMskBitp(Value)) { int N = Log2_32(Value) + 1; |